A80960CF33 Intel, A80960CF33 Datasheet - Page 35

• Manufacturer Part Number: A80960CF33
• Description: IC MPU I960CF 33MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CF33

• Processor Type: i960
• Features: CF suffix, 32-Bit with DMA, 4K Cache
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Family Name: 80960
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 168
• Package Type: CPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803084

4.5.1
Datasheet
Table 19. 80960CF AC Characteristics (25 MHz) (Sheet 3 of 3)
Figure 7. A.C. Test Load
A.C. Test Conditions
The AC Specifications in
load shown in
Specifications are measured at the 1.5 V crossing point, unless otherwise indicated. Input
waveforms are assumed to have a rise and fall time of < 2 ns from 0.8 V to 2.0 V. See
“A.C. Timing Waveforms” on page 36
illustrations.
NOTES:
10.These specifications must be met by the system for proper operation of the processor.
12.In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is
13.When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation
14.In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper
15.In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper
16.The interrupt pins are synchronized internally by the 80960CF . They have no required setup or hold times
Symbol
11. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of
1. 80960CF-25 only, per the conditions in
2. See
3. See
4. See
5. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus
6. N = Number of wait states inserted with READY.
7. Output Data and/or DT/R may be driven indefinitely following a cycle when there is no subsequent bus
8. Since asynchronous inputs are synchronized internally by the 80960CF, they have no required setup or
9. These specifications are ensured by the processor.
Conditions.
Controller Region Table. WAIT never goes active when there are no wait states in an access.
activity.
hold times to be recognized and for proper operation. However, to ensure recognition of the input at a
particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for
at least two consecutive PCLK2:1 rising edges to be seen by the processor.
Curves
operating. When the processor is in reset, the input clock may stop even in 1-x mode.
of less than ± 0.1% between adjacent cycles.
operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET
pin must meet setup and hold times to the falling edge of the CLKIN. (See
operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET
pin must meet setup and hold times to the rising edge of the CLKIN. (See
for proper operation. These pins are sampled by the interrupt controller every other clock and must be
active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To ensure
recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive
PCLK2:1 rising edges.
Section 4.5.2, A.C. Timing Waveforms
Figure 16
Figure 17
to adjust the timing for PCLK2:1 loading.
Figure
for capacitive derating information for output delays and hold times.
for capacitive derating information for rise and fall times.
7.
Figure 16
Section 4.5, “A.C. Specifications” on page 29
Parameter (1)
C
L
shows how timings vary with load capacitance.
= 50 pF for all signals
Output Pin
Section 4.2, Operating Conditions
for AC specification definitions, test points and
for waveforms and definitions.
C
L
F_CX008A
Min
and
Figure
Figure
are tested with the 50 pF
Section 4.5.1, A.C. Test
Max
24.)
23.)
Section 4.5.3, Derating
80960-40, -33, -25
Section 4.5.2,
Unit
Notes
35