MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 194

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.4.12 Transfer to/from Top of Stack Primitive
The transfer to/from top of stack primitive transfers an operand between the coprocessor
and the top of the active system stack of the main processor. This primitive applies to
general and conditional category instructions. Figure 7-32 shows the format of the transfer
to/from top of stack primitive.
The transfer to/from top of stack primitive uses the CA, PC, and DR bits as described in
7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues this
primitive with CA = 0 during a conditional category instruction, the main processor initiates
protocol violation exception processing.
The length field of the primitive format specifies the length in bytes of the operand to be
transferred. The operand may be one, two, or four bytes in length; other length values
cause the main processor to initiate protocol violation exception processing.
If DR = 0, the main processor transfers the operand from the active system stack to the
operand CIR. The implied effective address mode used for the transfer is the (A7)+
addressing mode. A one-byte operand causes the stack pointer to be incremented by two
after the transfer to maintain word alignment of the stack.
If DR = 1, the main processor transfers the operand from the operand CIR to the active
system stack. The implied effective address mode used for the transfer is the –(A7)
addressing mode. A one-byte operand causes the stack pointer to be decremented by two
before the transfer to maintain word alignment of the stack.
7.4.13 Transfer Single Main Processor Register Primitive
The transfer single main processor register primitive transfers an operand between one of
the main processor's data or address registers and the coprocessor. This primitive applies
to general and conditional category instructions. Figure 7-33 shows the format of the
transfer single main processor register primitive.
The transfer single main processor register primitive uses the CA, PC, and DR bits as
described in 7.4.2 Coprocessor Response Primitive General Format. If the
coprocessor issues this primitive with CA = 0 during a conditional category instruction, the
main processor initiates protocol violation exception processing.
MOTOROLA
Figure 7-33. Transfer Single Main Processor Register Primitive Format
15
CA
15
CA
Figure 7-32. Transfer to/from Top of Stack Primitive Format
PC
PC
14
14
DR
DR
13
13
12
12
0
0
11
11
1
1
10
10
1
1
M68020 USER’S MANUAL
9
1
9
0
8
8
0
0
7
7
0
6
0
5
0
4
LENGTH
0
D/A
3
2
REGISTER
0
0
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