MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 91

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

State 9
State 10
State 11
5.4 CPU SPACE CYCLES
FC2–FC0 select user and supervisor program and data areas as listed in Table 2-1. The
area selected by FC2–FC0 = 111 is classified as the CPU space. The interrupt
acknowledge, breakpoint acknowledge, module operations, and coprocessor
communication cycles described in the following paragraphs utilize CPU space.
The CPU space type is encoded on A19–A16 during a CPU space operation and indicates
the function that the processor is performing. On the MC68020/EC020, four of the
encodings are implemented as shown in Figure 5-31. All unused values are reserved by
Motorola for future use.
5-44
MC68020/EC020—The processor asserts DS during S9, indicating that the data on the
MC68020/EC020—The processor issues no new control signals during S10.
MC68020/EC020—The processor negates AS and DS during S11. It holds the address
data bus is stable. As long as at least one of the DSACK1/DSACK0 signals is
recognized by the end of S8 (meeting the asynchronous input setup time requirement),
the cycle terminates one clock later. If DSACK1/DSACK0 is not recognized by the start
of S9, the processor inserts wait states instead of proceeding to S10 and S11. To
ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated
throughout the asynchronous input setup and hold times around the end of S8. If wait
states are added, the processor continues to sample DSACK1/DSACK0 signals on the
falling edges of the clock until one is recognized.
The external device uses R/W , DS, SIZ1, SIZ0, A1, and A0 to latch data from the
appropriate section(s) of the data bus (D31–D24, D23–D16, D15–D8, and D7–D0).
SIZ1, SIZ0, A1, and A0 select the data bus sections. If it has not already done so, the
device asserts DSACK1/DSACK0 when it has successfully stored the data.
and data valid during S11 to provide address hold time for memory systems. R/W and
FC2–FC0 also remain valid throughout S11.
If more than one write cycle is required, S6–S11 are repeated for each write cycle.
The external device keeps DSACK1/DSACK0 asserted until it detects the negation of
AS or D S (whichever it detects first). The device must remove its data and negate
DSACK1/DSACK0 within approximately one clock period after sensing the negation of
AS or DS.
M68020 USER’S MANUAL
MOTOROLA