MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 224

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

CPU32+
IPIPE1–IPIPE0 should be sampled on the falling edge of the clock. Loading IRC always indi-
cates that an instruction is beginning execution — the opcode is loaded into IRC by the
transfer. In BDM mode, the data output DSO is connected to IPIPE0. The IPIPE1 pin is
unused in BDM mode.
5.6.3.3 OPCODE TRACKING DURING LOOP MODE. IPIPE and IFETCH continue to work
normally during loop mode. IFETCH indicates all instruction fetches up through the point that
data begins recirculating within the instruction pipeline. IPIPE continues to signal the start
of instructions and the use of extension words even though data is being recirculated inter-
nally. IFETCH returns to normal operation with the first fetch after exiting loop mode.
5.7 INSTRUCTION EXECUTION TIMING
This section describes the instruction execution timing of the CPU32+. External clock cycles
are used to provide accurate execution and operation timing guidelines, but not exact timing
for every possible circumstance. This approach is used because exact execution time for an
instruction or operation depends on concurrence of independently scheduled resources, on
memory speeds, and on other variables.
An assembly language programmer or compiler writer can use the information in this section
to predict the performance of the CPU32+. Additionally, timing for exception processing is
included so that designers of multitasking or real-time systems can predict task-switch over-
head, maximum interrupt latency, and similar timing parameters. Instruction timing is given
in clock cycles to eliminate clock frequency dependency.
Most instruction timing information in the following subsections is taken from the CPU32
documentation. It applies to the CPU32+ when it is executing in 16-bit mode. However, a
summary of experiments run on the CPU32+ and the CPU32 is given in Table 5-25. The
tests show general indications of performance improvement of the CPU32+ over the
CPU32. Actual results on real applications may vary.
Note that the CPU32+ gains a significant performance advantage (58%) over the original
CPU32 when using long operands on a slow external bus. (Most compilers generate code
using long operands where possible.) Thus, the CPU32+ performance in 32-bit mode "falls
off" less rapidly than does the original CPU32.
5-82
16-Bit Data Bus
32-Bit Data Bus with 16-Bit Operands Only
32-Bit Data Bus with 32-Bit Operands Only
NOTE:
PI = % Performance Increase over a CPU32 in the same conditions
BU = % Bus Utilization taken by the processor in the experiment
(e.g., MOVE.W, CLR.W, etc.)
(e.g., MOVE.L, MOVEA.L, MOVEM.L etc.)
Table 5-25. CPU32+ Performance Improvement over the CPU32
Conditions
Freescale Semiconductor, Inc.
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13/50
6/52
0/78
2
Bus Cycle Length
PI/BU (see Note)
13/65
40/62
0/89
3
24/76
58/73
MOTOROLA
0/95
5