MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 339

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.4.7 RISC Timer Initialization Example
The following sequence initializes RISC timer 0 to generate an interrupt approximately every
second using a 25-MHz general system clock:
MOTOROLA
2. Determine the maximum number of timers to be located in the timer table and config-
3. Clear the TM_cnt in the RISC timer table parameter RAM to show how many ticks
4. Clear the RISC timer event register if it is not already cleared. (Ones are written to
5. Configure the RTMR to enable those timers that should generate interrupts. (Ones en-
6. Set the RISC timer table bit in the CPM interrupt mask register to generate interrupts
7. Configure the TM_cmd field of the RISC timer table parameter RAM. At this point, de-
8. Issue the SET TIMER command by writing $0861 to the CR.
9. Repeat the preceding two steps for each timer to be enabled or disabled.
1. Write the TIMEP bits of the RCCR with 111111 to generate the slowest clock. This val-
2. Configure TM_BASE in the RISC timer table parameter RAM to point to a location in
3. Write $0000 to TM_cnt in the RISC timer table parameter RAM to see how many ticks
4. Write $FFFF to the RTER to clear any previous events.
5. Write $0001 to the RTMR to enable RISC timer 0 to generate an interrupt.
6. Write $00020000 to the CPM interrupt mask register to allow the RISC timers to gen-
7. Write $C0000EE6 to the TM_cmd field of the RISC timer table parameter RAM. This
8. Write $0851 to the CR to issue the SET TIMER command.
9. Set the TIME bit in the RCCR to enable the RISC timer to begin operation.
tire timer table. The TIME bit would normally be turned on at this time; however, it can
be turned on later if it is required that all RISC timers be synchronized.
ure TM_BASE in the RISC timer table parameter RAM to point to a location in the dual
port RAM with 4 N bytes available, where N is the number of timers. If N is less than
16, use timer 0 through timer N–1 (for space efficiency).
have elapsed since the RISC internal timer was enabled. This step is optional.
clear this register.)
able interrupts.)
to the system. (The CPM interrupt controller may require other initialization not men-
tioned here.)
termine whether a timer is to be enabled or disabled, one-shot or restart, and what its
timeout period should be. If the timer is being disabled, the parameters (other than the
timer number) are ignored.
ue will generate a tick every 65536 clocks, which is every 2.6 ms at 25 MHz.
the dual-port RAM with 4 bytes available. Assuming the beginning of dual-port RAM is
available, write $0000 to TM_BASE.
have elapsed since the RISC internal timer was enabled. This step is optional.
erate a system interrupt. Initialize the CPM interrupt configuration register.
enables RISC timer 0 to time out after 3814 (decimal) ticks of the timer. The timer will
automatically restart after it times out.
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RISC Timer Tables
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