MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 597

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

MOT—Motorola
FC3–FC0—Function Code 3–0
7.11.4.3 MAXIMUM RECEIVE BUFFER LENGTH REGISTER (MRBLR). Each SMC has
one MRBLR to define the receive buffer length for that SMC. MRBLR defines the maximum
number of bytes that the QUICC will write to a receive buffer on that SMC before moving to
the next buffer. The QUICC may write fewer bytes to the buffer than MRBLR if a condition
such as an error or end-of-frame occurs, but it will never write more bytes than the MRBLR
value. It follows, then, that buffers supplied by the user for use by the QUICC should always
be of size MRBLR (or greater) in length.
The transmit buffers for an SMC are not affected in any way by the value programmed into
MRBLR. Transmit buffers may be individually chosen to have varying lengths, as needed.
The number of bytes to be transmitted is chosen by programming the data length field in the
Tx BD.
7.11.4.4 RECEIVER BUFFER DESCRIPTOR POINTER (RBPTR). The RBPTR for each
SMC channel points to the next BD that the receiver will transfer data to when it is in idle
state or to the current BD during frame processing. After a reset or when the end of the BD
table is reached, the CP initializes this pointer to the value programmed in the RBASE entry.
MOTOROLA
This bit should be set by the user to achieve normal operation. MOT must be set if the
data buffer is located in external memory and has a 16-bit wide memory port size.
These bits contain the function code value used during this SDMA channel’s memory ac-
cesses. The user should write bit FC3 with a one to identify this SDMA channel access as
a DMA-type access. Example: FC3–FC0 = 1000 (binary). Do not write the value 0111 (bi-
nary) to these bits.
0 = DEC (and Intel) convention is used for byte ordering—swapped operation. It is also
1 = Motorola byte ordering—normal operation. It is also called big-endian byte order-
called little-endian byte ordering. The transmission order of bytes within a buffer
word is reversed as compared to the Motorola mode.
ing. As data is transmitted onto the serial line from the data buffer, the most signif-
icant byte of the buffer word contains data to be transmitted earlier than the least
significant byte of the same buffer word.
MRBLR should not be changed dynamically while an SMC is op-
erating. However, if it is modified in a single bus cycle with one
16-bit move (not two 8-bit bus cycles back-to-back), then a dy-
namic change in receive buffer length can be successfully
achieved. This occurs when the CP moves control to the next Rx
BD in the table. Thus, a change to MRBLR will not have an im-
mediate effect. To guarantee the exact Rx BD on which the
change will occur, the user should change MRBLR only while
the SMC receiver is disabled.
The MRBLR value should be greater than zero, and should be
even if the character length of the data is greater than 8 bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
Serial Management Controllers (SMCs)
7-273