MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 247

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The QUICC also provides the ability to request and obtain mastership of the system bus.
This logic is only reset during a power-on reset and is active at all other times. See Section
4 Bus Operation for further discussion.
The QUICC includes dedicated user-accessible test logic that is fully compliant with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. This standard
was developed under the sponsorship of the IEEE Test Technology Committee and Joint
Test Action Group (JTAG). The QUICC implementation supports circuit-board test strate-
gies based on this standard. Refer to Section 8 Scan Chain Test Access Port for additional
information.
The following paragraphs describe the operation of the MBAR, system configuration and
protection, clock synthesizer, breakpoint logic, slave mode, and EBI control.
6.2 MODULE BASE ADDRESS REGISTER (MBAR)
The MBAR controls the location of all module registers (see 6.9.1 Module Base Address
Register (MBAR)). The address stored in this register is the base address (starting location)
for the internal module registers. All internal module registers and RAM occupy a single 8-
kbyte memory block (see Figure 6-1) that is relocatable along 8-Kbyte boundaries. The loca-
tion of the internal registers is fixed by writing the desired base address of the 8-Kbyte block
to the MBAR using the MOVES instruction to address $0003FF00 in CPU space. The
source function code (SFC) and destination function code (DFC) registers contain the
address space values (FC2–FC0) for the read or write operand of the MOVES instruction
(see Section 5 CPU32+ or M68000PM/AD, Programmer’s Reference Manual ). Therefore,
the SFC or DFC register must indicate CPU space (FC2–FC0 = $7), using the MOVEC
instruction, before accessing the MBAR.
6.3 SYSTEM CONFIGURATION AND PROTECTION
The SIM60 allows the user to control certain features of system configuration by writing bits
in the module configuration register (MCR).
All M68000 family members are designed to provide maximum system safeguards. As an
extension of the family, the QUICC promotes the same basic concepts of safeguarded
design present in all M68000 members. In addition, many functions that normally must be
provided in external circuits are incorporated in this device. The following features are pro-
vided in the system configuration and protection sub-module:
SIM60 Configuration
Reset Status
MOTOROLA
The SIM60 allows the user to configure the system according to the particular require-
ments. The functions include control of slave mode (disable CPU32+) operation, freeze
and show cycle operation, the access privilege of the supervisor/user registers, the level
of interrupt arbitration, and automatic autovectoring for external interrupts.
The reset status register provides the user with information on the cause of the most re-
cent reset. The possible causes include external, power-up, software watchdog, double
bus fault, loss of clock, and the RESET instruction.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
System Integration Module (SIM60)
6-3