MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 646

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Peripheral Interface (SPI)
Bits 7–5—Reserved.
MOT—Motorola
FC3–FC0—Function Code 3–0
7.12.5.3.3 Maximum Receive Buffer Length Register (MRBLR). The
MRBLR to define the receive buffer length for that SPI. MRBLR defines the maximum num-
ber of bytes that the QUICC will write to a receive buffer on that SPI before moving to the
next buffer. The QUICC may write fewer bytes to the buffer than the MRBLR value if a con-
dition such as an error or end-of-frame occurs, but it will never write more bytes than the
MRBLR value. It follows, then, that buffers supplied by the user for use by the QUICC should
always be of size MRBLR (or greater) in length.
The transmit buffers for an SPI are not affected in any way by the value programmed into
MRBLR. Transmit buffers may be individually chosen to have varying lengths, as needed.
The number of bytes to be transmitted is chosen by programming the data length field in the
Tx BD.
7-322
This bit should be set by the user to achieve normal operation. MOT must be set if the
data buffer is located in external memory and has a 16-bit wide memory port size.
These bits contain the function code value used during this SDMA channel’s memory ac-
cesses. The user should write bit FC3 with a one to identify this SDMA channel access as
a DMA-type access. Example: FC3-FC0 = 1000. To keep interrupt acknowledge cycles
unique in the system, do not write the value 0111 (binary) to these bits.
These bits should be set to zero by the user.
0 = DEC and Intel convention is used for byte ordering—swapped operation. It is also
1 = Motorola byte ordering—normal operation. It is also called big-endian byte order-
called little-endian byte ordering. The transmission order of bytes within a buffer
word is reversed as compared to the Motorola mode.
ing. As data is transmitted onto the serial line from the data buffer, the most signif-
icant byte of the buffer word contains data to be transmitted earlier than the least
significant byte of the same buffer word.
MRBLR is not intended to be changed dynamically while an SPI
is operating. However, if it is modified in a single bus cycle with
one 16-bit move (NOT two 8-bit bus cycles back-to-back), then
a dynamic change in receive buffer length can be successfully
achieved. This takes place when the CP moves control to the
next Rx BD in the table. Thus, a change to MRBLR will not have
an immediate effect. To guarantee the exact Rx BD on which the
change will occur, the user should change MRBLR only while
the SPI receiver is disabled.
The MRBLR value should be greater than zero and should be
even if the character length of the data is greater than eight bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
SPI
MOTOROLA
has
one