MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet
MC68MH360ZP25VL
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... Freescale Semiconductor, Inc. QMC Memory Organization Features Deleted in MC68MH360 Multi-Subchannel (MSC) Microcode 68360 Bit Numbering Frequently-Asked Questions Connecting ISDN Interfaces to QUICC32 For More Information On This Product, Go to: www.freescale.com Overview 1 2 QMC Commands 3 QMC Exceptions 4 Buffer Descriptors 5 QMC Initialization 6 7 Performance Index ...
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... Freescale Semiconductor, Inc. Overview 1 QMC Memory Organization 2 QMC Commands 3 4 QMC Exceptions Buffer Descriptors 5 6 QMC Initialization 7 Features Deleted in MC68MH360 Performance 8 Multi-Subchannel (MSC) Microcode 9 68360 Bit Numbering A Frequently-Asked Questions B C Connecting ISDN Interfaces to QUICC32 Index IND For More Information On This Product, ...
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... Freescale Semiconductor, Inc. QMC Supplement to MC68360 and MPC860 User’s Manuals For More Information On This Product, Go to: www.freescale.com QMCSUPPLEMENT/AD 8/97 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
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... Freescale Semiconductor, Inc. CONTENTS Paragraph Number Audience ................................................................................................................ xi Organization........................................................................................................... xi Additional Reading ............................................................................................... xii Conventions .......................................................................................................... xii Acronyms and Abbreviations .............................................................................. xiii 1.1 The QMC (QUICC Multichannel Controller) ..................................................... 1-1 1.2 Introduction.......................................................................................................... 1-1 1.3 QMC Features...................................................................................................... 1-3 1.4 The Time Slot Assigner and the QMC ................................................................ 1-4 1.5 The Serial Interface (SI) ...
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... Freescale Semiconductor, Inc. CONTENTS Paragraph Number 2.1.9 Data Buffer .......................................................................................................2-5 2.2 Global Multichannel Parameters ..........................................................................2-5 2.3 Multiple SCC Assignment Tables ......................................................................2-10 2.4 Channel-Specific Parameters..............................................................................2-14 2.4.1 Channel-Specific HDLC Parameters..............................................................2-14 2.4.1.1 CHAMR—Channel Mode Register (HDLC).............................................2-15 2.4.1.2 TSTATE—Tx Internal State (HDLC)........................................................2-17 2.4.1.3 INTMSK— ...
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... Freescale Semiconductor, Inc. CONTENTS Paragraph Number 5.3.4 MC68MH360 Configured for QMC and Ethernet.........................................5-20 QMC Initialization 6.1 Initialization Steps................................................................................................6-1 6.2 68MH360 T1 Example.......................................................................................6-10 6.3 Restarting the Transmitter..................................................................................6-17 6.4 Restarting the Receiver ......................................................................................6-17 6.5 Disabling Receiver and Transmitter...................................................................6-17 6.6 Debugging Hints ...
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... Freescale Semiconductor, Inc. CONTENTS Paragraph Number A.5 SCC Event Register .............................................................................................A-5 A.6 SCCM Register....................................................................................................A-5 A.7 Receive and Transmit Buffer Descriptors ...........................................................A-5 Frequently-Asked Questions B.1 Questions Common to MH360 and 860MH........................................................B-1 B.2 860MH-Related Questions ..................................................................................B-2 B.3 MH360-Related Questions ..................................................................................B-4 Connecting ISDN Multiple S Interfaces to QUICC32 C ...
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... Freescale Semiconductor, Inc. ILLUSTRATIONS Figure Number 1-1 QMC Channel Addressing Capability ............................................................................. 1-2 1-2 Ethernet-to-BRI Bridge Using MC68EN360................................................................... 1-6 1-3 Internal Routing for Ethernet-to-BRI Bridge Using MC68EN360.................................. 1-7 1-4 Ethernet-to-BRI Bridge Using MC68MH360 ................................................................. 1-8 1-5 Internal Routing for Ethernet-to-BRI Bridge Using MC68MH360 ................................ 1-8 1-6 Ethernet-to-PRI Bridge Using MPC860MH ...
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... Freescale Semiconductor, Inc. ILLUSTRATIONS Figure Number 5-7 MC68MH360 SCC1 Parameter RAM Usage ................................................................ 5-10 5-8 MC68MH360 SCC2 Parameter RAM Usage ................................................................ 5-11 5-9 MC68MH360 SCC3 Parameter RAM Usage ................................................................ 5-12 5-10 MC68MH360 SCC4 Parameter RAM Usage ................................................................ 5-13 5-11 MPC860MH Internal Memory ...................................................................................... 5-14 5-12 MPC860MH SCC1 Parameter RAM Usage.................................................................. 5-16 5-13 MPC860MH SCC2 Parameter RAM Usage ...
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... Freescale Semiconductor, Inc. Table Number i Acronyms and Abbreviated Terms .................................................................................. xiii 2-1 Global Multichannel Parameters...................................................................................... 2-5 2-2 Time Slot Assignment Table Entry Fields for Receive Section ...................................... 2-9 2-3 Time Slot Assignment Table Entry Fields for Transmit Section..................................... 2-9 2-4 Channel-Specific HDLC Parameters ............................................................................. 2-14 2-5 CHAMR Field Descriptions (HDLC) ...
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... Freescale Semiconductor, Inc. Table Number 9-1 Time Slot Assignment Table Entry Fields for Receive (MSC) ....................................... 9-4 9-2 Time Slot Assignment Table Entry Fields for Transmit (MSC)...................................... 9-5 B-1 CPU Performance ............................................................................................................B-1 C-1 TCLK Frequencies Selected by BR13[5] and BR7[2] ....................................................C-5 For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. About This Book This document is a supplement to the MC68360 Quad Integrated Communications Controller User’s Manual (MC68360UM/AD) and the MPC860 PowerQUICC User’s Manual (MPC860UM/AD). It replaces the MC68MH360 Reference Manual (MC68MH360RM/AD). To locate any published errata or updates for this document, refer to the website at http://www ...
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... Freescale Semiconductor, Inc. • Chapter 9, “Multi-Subchannel (MSC) Microcode,” provides the MSC microcode features and operation, and discusses how to program the MSC protocol. • Appendix A, “68360 Bit Numbering,”shows the bit numbering used for the 68360. • Appendix B, “Frequently-Asked Questions,” provides a list of common questions and solutions for the MH360 and 860MH. • ...
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... Freescale Semiconductor, Inc. Acronyms and Abbreviations Table i contains acronyms and abbreviations that are used in this document. Table i. Acronyms and Abbreviated Terms Term BD Buffer descriptor bps Bits per second BRI Basic rate interface BRG Baud rate generator CPM Communications processor module CR Command register ...
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... Freescale Semiconductor, Inc. QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 1 Overview 10 10 This chapter gives an overview of the QMC protocol including some example applications. 1.1 The QMC (QUICC Multichannel Controller) The QMC protocol emulates logical channels within one SCC (serial communication controller) using the same time-division-multiplexed (TDM) physical interface. This multichannel protocol is implemented using the CPM ROM space and additional hardware ...
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... Freescale Semiconductor, Inc. works transparently, not participating in any QMC protocol functions. The SCC only performs the parallel-to-serial conversion and adds elasticity through its FIFO memory. The CPM, with its special enhanced microcode and additional dedicated hardware for framing and masking support, does all of the protocol processing for each of the 64 channels. Note that it is executed without intervention from the on-board CPU. Figure 1-1 illustrates the QMC’ ...
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... Freescale Semiconductor, Inc. 1.3 QMC Features • MC68MH360-specific features — independent communication channels — Arbitrary mapping of any of 0–31 channels to any of 0–31 TDM time slot — Can support arbitrary mapping of any of 0–31 channels to any of 0–63 TDM time slots in case of common Rx and Tx mapping — ...
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... Freescale Semiconductor, Inc. • System interface — On-chip bus arbitration for serial DMAs with no performance penalty — Efficient bus usage (no bus usage for nonactive channels and active channels that have nothing to transmit) — Efficient control of the interrupts to the CPU — Supports external buffer descriptors table — ...
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... Freescale Semiconductor, Inc. 1.5.1 Synchronization Independent receive and transmit clocks and frame synchronization signals control the data transfer. In NMSI operation, synchronization occurs only once to initiate a transfer using the CD (receive) and CTS (transmit) signals in pulse mode. If any noise corrupts either signal, the QMC will be out of synchronization until the whole protocol is restarted. ...
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... Freescale Semiconductor, Inc. 1.6 QMC Serial Routing and Example Applications The QMC protocol provides multiple logical channels from a single SCC. The SCC channel dedicated to operate the QMC protocol should have all the relevant bits or time slots routed to it. Individual logical channels are selected by a combination of signals routed through the TDM and tables within the QMC protocol. Contrasting a non-QMC example application with QMC implementations highlights benefi ...
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... Freescale Semiconductor, Inc SCC1 SCC2 SCC3 TSA NMSI Ethernet B1 B2 BRI ISDN Figure 1-3. Internal Routing for Ethernet-to-BRI Bridge Using MC68EN360 The following example shows how an MC68MH360 can implement the BRI using only one SCC, leaving SCC3 and SCC4 available to run other protocols such as frame relay over HDLC and another Ethernet link, on SCC1, to the LAN. The QMC protocol allows all three channels B1, B2, and routed to SCC2 using the TSA. The fi ...
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... Freescale Semiconductor, Inc. MC68MH360 TSA 4-wire IDL2 SCC2 ISDN MC145574 line SPI SCC3 SCC4 Figure 1-4. Ethernet-to-BRI Bridge Using MC68MH360 SCC1 SCC2 SCC3 NMSI TSA Ethernet B1 Figure 1-5. Internal Routing for Ethernet-to-BRI Bridge Using MC68MH360 Figure 1-6 and Figure 1-7 show how to build a PRI ISDN-to-Ethernet bridge using an MPC860MH. SCC1 is used for the Ethernet channel. SCC2 is confi ...
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... Freescale Semiconductor, Inc. MP860MH Dallas Semiconductor ISDN Framer TSA 4-wire SCC2 ISDN DS2180A line SPI SCC4 SCC2 Figure 1-6. Ethernet-to-PRI Bridge Using MPC860MH D B30 Memory SCC1 SCC2 SCC3 NMSI TSA Ethernet PRI ISDN B1 B2 B30 Figure 1-7. Internal Routing for Ethernet-to-PRI Bridge Using MPC860 Chapter 1 ...
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... Freescale Semiconductor, Inc. 1.7 SCC Changes on the Fly Changes can be made on the fly in the QMC routing tables, but changes made in the SI RAM require the link to be disconnected. If the connection is maintained during changes, synchronization and routing errors are likely to happen in the current frame. A workaround uses a shadow RAM routing table ...
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... Freescale Semiconductor, Inc clock pulse is missing in a given frame N, the counter will fail to reach its end state before the next sync pulse (N+1) arrives, causing that sync pulse to be ignored. When the counter finally reaches its end state, it waits for the next sync pulse (N+2) before resetting. ...
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... Freescale Semiconductor, Inc. Frame Structure for E1 2.048 Mbps Framing (TS0) FRAME STRUCTURE FOR T1 1.544 MBPS Framing Bit 193 Figure 1-8. Frame Structures for E1/CEPT and T1 TDM Interfaces For any station to receive and transmit on a TDM line necessary for it to determine the correct time slot boundary ...
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... Freescale Semiconductor, Inc. A framer device will retrieve the 8-KHz frame synchronization pulses and clock signals for both transmit and receive sections. A time slot assigner will use these signals as inputs to generate pulses or envelope signals for individual bit patterns, i.e., strobe signals for devices without time slot assignment capability such as the MC68302, a fi ...
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... Freescale Semiconductor, Inc. QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 2 QMC Memory Organization 20 20 This section describes the operation specific to the QMC protocol. When not running the QMC protocol, SCCs operate as described in the MC68360 and MPC860 user’s manuals. Figure 2-1 shows the dual-ported RAM structure for the MC68MH360 and the MPC860MH ...
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... Freescale Semiconductor, Inc. 2.1 QMC Memory Structure Figure 2-2 shows how data is addressed by the QMC protocol. It discusses addressing the dual-ported RAM to access data within the buffers. Figure 2-2. QMC Memory Structure For More Information On This Product, Go to: www.freescale.com QMC Supplement ...
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... Freescale Semiconductor, Inc. 2.1.1 Dual-Ported RAM Base The MC68MH360’s internal memory is mapped into an 8-Kbyte block of memory, and the starting address is dictated by the DPRBASE programmed in the MBAR register. For more detail on the QUICC internal memory structure, see Section 3 of MC68360 Quad Integrated Communications Controller User’ ...
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... Freescale Semiconductor, Inc. 2.1.4 TSATRx/TSATTx Channel Pointers The channel pointers are 12-bit pointers to the channel-specific parameters in the internal dual-ported RAM. These should not be confused with TSATRx/TSATTx pointers as described in Section 2.1.3, “TSATRx/TSATTx Pointers and Time Slot Assignment Table.” The 6 most-significant bits of the address are taken from the time slot assignment table. For the MH360, the most-signifi ...
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... Freescale Semiconductor, Inc. 2.1.8 Data Buffer Pointer As with the standard CPM protocols, the data buffer is addressed by a 32-bit pointer within the buffer descriptor. This addresses the data received or transmitted from external memory. 2.1.9 Data Buffer The data buffers in external memory can hold Kbytes of data as determined by the data length in the buffer descriptor ...
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... Freescale Semiconductor, Inc. Table 2-1. Global Multichannel Parameters (Continued) Offset to Width Name SCC (Bits) Base 06 MRBLR 16 Maximum receive buffer length—This host-initialized entry defines the maximum number of bytes written to a receive buffer before moving to the next buffer for this channel. This parameter is only valid in HDLC mode. ...
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... Freescale Semiconductor, Inc. Table 2-1. Global Multichannel Parameters (Continued) Offset to Width Name SCC (Bits) Base 18 Rx_S_PTR 16 Rx time-slot assignment table pointer (default = SCC base + 20 in normal mode)—This global QMC parameter defines the start value of the TSATRx table, which must be present only once per SCC global area. Other SCCs may access this location ...
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... Freescale Semiconductor, Inc. The area between SCC base + 20 and SCC base + 9F is normally used for TSA tables. The mapping above is ideal for 32-channel support. The exact mapping of the TSA tables is determined by the programming of Rx_S_PTR and Tx_S_PTR, and is not fixed. For 64-channel support it is suggested to use common Rx and Tx parameters ...
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... Freescale Semiconductor, Inc. Table 2-2 describes the fields in the time slot assignment table for receive. Table 2-2. Time Slot Assignment Table Entry Fields for Receive Section Field V Valid bit—The valid bit indicates whether this time slot is valid. 0 The data in this 8-bit time slot is totally ignored and not written to any buffer. ...
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... Freescale Semiconductor, Inc. If the transmitter and receiver have the same mapping then it is possible to use a common time slot assignment table. This is initialized by setting both Tx_S_PTR and Rx_S_PTR to SCC Base + 20. For 64-channel support it is suggested to use common Rx and Tx parameters. The time slot assignment table will then also be common and have 64 entries starting at SCC Base + 20 ...
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... Freescale Semiconductor, Inc. TSA 0 SCC3 SCC2 SCC Base +0x20 CPM SCC2 Parameter RAM Rx_S_PTR_2 Time Slot Assignment Table Rx_2 SCC3 Parameter RAM Rx_S_PTR_3 Time Slot Assignment Table Rx_3 (not used) Figure 2-5. Rx Time Slot Assignment Table for 32 Channels over Two SCCs It is important that multiples of bytes are routed to each SCC to delineate between time slots ...
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... Freescale Semiconductor, Inc. In Figure 2-5, each SCC has its own pointer, Rx_S_PTR_2 and Rx_S_PTR_3, addressing SCC2’s time slot assignment table. This table only needs to be present once in one of the SCC2’s global parameter area. Rx_S_PTR_2 points to the start of the table, address SCC base + 20. The 16 logical channels from SCC2 are located in the fi ...
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... Freescale Semiconductor, Inc. TSA SCC3 SCC2 CPM SCC2 Parameter RAM Tx_S_PTR_2 Rx_S_PTR_2 Time Slot Assignment Table Rx Located in SCC 2 parameter RAM SCC3 Parameter RAM Tx_S_PTR_3 Rx_S_PTR_3 SCC3 Base + 0x20 Time Slot Assignment Table Rx Located in SCC3 parameter RAM SCC3 Base +0x60 Common TSATTx located in SCC3 Parameter RAM Figure 2-6 ...
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... Freescale Semiconductor, Inc. 2.4 Channel-Specific Parameters The channel-specific parameters are located in the lower part of the dual-ported RAM. Each channel occupies 64 bytes of parameters. Physical time slots can be matched to logical channels in several combinations. Unused logical channels leave a hole in the channel- specific parameters that can be used for buffer descriptors for the other SCCs. ...
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... Freescale Semiconductor, Inc. Table 2-4. Channel-Specific HDLC Parameters (Continued) Width Offset Name (Bits) 22 MFLR 16 Maximum frame length register (host-initialized)—Defines the longest expectable frame for this channel. Its maximum value is 64 Kbytes. The remainder of a frame which is larger than MFLR is discarded and a flag in the last frame’ set (LG). ...
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... Freescale Semiconductor, Inc. Table 2-5 describes the channel mode register’s fields for HDLC operation. Boldfaced parameters must be initialized by the user. Table 2-5. CHAMR Field Descriptions (HDLC) Field Name 0 MODE Mode—Each channel has a programmable option whether to use transparent mode or HDLC mode ...
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... Freescale Semiconductor, Inc. Table 2-5. CHAMR Field Descriptions (HDLC) (Continued) Field Name 10–11 — Reserved 12–15 NOF Number of flags—Defines the minimum number of flags before frames. However, even if NOF = 0, at least one flag is transmitted before the first frame. See the description of the IDLM bit for more information. 2.4.1.2 TSTATE— ...
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... Freescale Semiconductor, Inc. Table 2-7. TSTATE Field Descriptions for 860MH (HDLC) Field Name 0–1 — — MOT Motorola/Intel bit 0 = The bus format is Intel format (little-endian The system bus is considered to be organized in Motorola format (big-endian). 4 — 0 5–7 AT[1–3] Address type—This field contains the address type for the transmitter DMA channel for data buffers in external memory (transmit buffers) ...
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... Freescale Semiconductor, Inc. 2.4.1.4 RSTATE—Rx Internal State (HDLC) Host-initialized to 0x3900_0000 before enabling the channel or after a fatal error (that is, global overrun, busy) or after a STOP Rx command. The high byte of RSTATE defines the function code/address type and the Motorola/Intel bit. Bit 3 (or bit 28 for the 68360) should always be set to 1. Figure 2-10 shows the RSTATE register for HDLC operation ...
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... Freescale Semiconductor, Inc. Table 2-9. RSTATE Field Descriptions for 860MH (HDLC) Field Name 0–1 — — MOT Motorola/Intel bit 0 = The bus format is Intel format (little-endian The system bus is considered to be organized in Motorola format (big-endian). 4 — 0 5–7 AT[1–3] Address type—This field contains the address type for the transmitter DMA channel for data buffers in external memory (transmit buffers) ...
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... Freescale Semiconductor, Inc. Table 2-10. Channel-Specific Transparent Parameters (Continued) Offset Name Width 22 TMRBLR 16 Transparent maximum receive buffer length (host-initialized entry)—Defines the maximum number of bytes written to a receive buffer before moving to the next buffer for this channel. Note that this value must be a multiple of 4 bytes as the QMC works on long-word alignment ...
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... Freescale Semiconductor, Inc. Table 2-11. CHAMR Bit Settings (Transparent Mode) Field Name 0 MODE Mode—Each channel has a programmable option whether to use transparent mode or HDLC mode. 0 Transparent mode 1 HDLC mode 1 RD Reverse data 0 The bit order will not be reversed, transmitting/receiving the LSB of each octet first. ...
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... Freescale Semiconductor, Inc. 2.4.2.2 TSTATE—Tx Internal State (Transparent Mode) TSTATE defines the internal transmitter state. The high byte of TSTATE defines the function code/address type and the Motorola/Intel bit (bit 3) that should always be set to 1. Figure 2-12 shows the TSTATE register for transparent mode. ...
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... Freescale Semiconductor, Inc. 2.4.2.3 INTMSK—Interrupt Mask (Transparent Mode) Each event defined in the interrupt circular queue entry maps directly to a bit in INTMSK as shown in Figure 2-13. There is one mask bit for each event—UN (bit 11), BSY (bit 13), TXB (bit 14) and RXB (bit 15). Bits that do not map to an event are reserved. Reserved bits must be set to zero. • ...
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... Freescale Semiconductor, Inc. Take the example of a superchannel of several time slots: TSn, TSn + 1, TSn + 2 ....... TSn + x The algorithm for the receiver byte in decimal is: (TSn + The algorithm for the transmit byte in decimal is: (TSn + The result from these calculations is a decimal value programmed into TRNSYNC. ...
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... Freescale Semiconductor, Inc 2-byte pattern TS8, TS7, so TSn = 8 Rx Byte: (8+ TSn + Byte 2-byte pattern TS19, TS23, so TSn = 19 Rx Byte: ( TSn + Byte: ( 2-byte pattern TS23, TS19, so TSn = 23 Rx Byte: ( TSn + x = 19, so; TX Byte: ( 4-byte pattern TS20, TS23, TS8, TS9 & TS19, so TSn = 20 ...
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... Freescale Semiconductor, Inc. SINGLE CHANNEL IN TS7 C1 7 SINGLE CHANNEL IN TS23 C2 DUAL CHANNEL DUAL CHANNEL IN TS7 DUAL CHANNEL IN TS19+23 C5 DUAL CHANNEL IN TS19+23 C6 MULTI CHANNEL IN TS8+9+19+20+ MULTI CHANNEL IN TS8+9+19+20+ MULTI CHANNEL IN TS8+9+19+20+ Figure 2-14. Examples of Different T1 Time Slot Allocation Chapter 2. QMC Memory Organization For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. 2.4.2.5 RSTATE—Rx Internal State (Transparent Mode) The RSTATE is host-initialized before enabling the channel or after a fatal error (that is, global overrun, busy) or after a STOP Rx command. The high byte of RSTATE defines the function code/address type and the Motorola/Intel bit. Bit 3 (or bit 29 for the 68360) should always be set to 1. Figure 2-15 shows the RSTATE register for transparent mode ...
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... Freescale Semiconductor, Inc. For the 860MH, RSTATE should be initialized to 0x3100_0000 before enabling the channel — Note that for the 860MH, bit 4 should always be zero as only bits 5–7 map to AT[1–3]. Table 2-15 describes the RSTATE fields for the 860MH with boldfaced parameters to be initialized by the user ...
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... Freescale Semiconductor, Inc. QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 3 QMC Commands 30 30 The host issues commands to the QMC by writing to the command register (CR). The QMC commands are similar to those of standard QUICC HDLC protocol. The CR format for QMC is shown in Figure 3- RST QMC OPCODE Note: For the 68360, the bit numbering is reversed. See Appendix A for more information. ...
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... Freescale Semiconductor, Inc. 3.2 Receive Commands STOP RECEIVE <channel> (QMC opcode = 000) The stop receive command forces the receiver of the selected channel to stop receiving. After issuing this command, the microcode does not change any of the receive parameters in the dual-ported RAM. Initialize ZDSTATE and RSTATE to their initial values to start reception or to continue receiving after a stop command ...
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... Freescale Semiconductor, Inc. Chapter 4 QMC Exceptions 40 40 QMC interrupt handling involves two principle data structures—the SCC event register (SCCE) and the circular interrupt table. Figure 4-1 illustrates the circular interrupt table. INTBASE SOFTWARE POINTER INTPTR Figure 4-1. Circular Interrupt Table in External Memory ...
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... Freescale Semiconductor, Inc. Following a request that is not masked out by the INTMASK or the SCCM (SCC mask) register, an interrupt is generated to the host. The host reads the SCCE to determine the cause of interrupt. A dedicated SCCE bit (GINT) indicates that at least one new entry was added to the queue. After clearing GINT, the host starts processing the queue. The host then clears this entry’ ...
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... Freescale Semiconductor, Inc. 4.1.1 Global Underrun (GUN) The QMC performs the following actions when it detects a GUN event: • Transmits an abort sequence of minimum sixteen 1’s in each time slot. • Generates an interrupt request to the host (if enabled) and sets the GUN bit in the SCCE register. ...
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... Freescale Semiconductor, Inc Note: For the 68360, the bit numbering is reversed. See Appendix A for more information. Figure 4-2. SCC Event Register Table 4-1 SCC Event Register Field Descriptions . Field Name 0–3 — Reserved 4 IQOV Interrupt table (interrupt queue) overfl interrupt table overflow has occurred. ...
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... Freescale Semiconductor, Inc Note: For the 68360, the bit numbering is reversed. See Appendix A for more information. Figure 4-3. SCCM Register 4.3 Interrupt Table Entry The interrupt table contains information about channel-specific events. Its flags are shown in Figure 4-4. Note that some bits have no meaning when operating in transparent mode. ...
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... Freescale Semiconductor, Inc. Table 4-2. Interrupt Table Entry Field Descriptions (Continued) Field Name 3 IDL Idle IDL event has occurred The channel’s receiver has identified the first occurrence of HDLC idle (FFFE) after any non-idle pattern. IDL interrupts are not generated in transparent mode. ...
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... Freescale Semiconductor, Inc. Table 4-2. Interrupt Table Entry Field Descriptions (Continued) Field Name 14 TXB Tx buffer TXB event has occurred buffer has been completely transmitted. This bit is set (and an interrupt request is generated) as soon as the programmed number of PAD characters (or the closing flag, for PAD = 0) is written to the SCC’ ...
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... Freescale Semiconductor, Inc. Start Interrupt Interrupt masked in occurs INTMSK? N INTPTR->CITentry.V Set SCCEx.IQOV = End Make new entry including V =1; increment INTPTR Y Decrement RxF event GRFCNT ? N Set SCCEx.GINT End Figure 4-5. Channel Interrupt Flow QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 5 Buffer Descriptors 50 50 QMC buffer descriptors are located within 64 Kbytes in external memory; see Figure 2-2. Each buffer descriptor contains key information about the buffer it defines. The first two sections describe the contents of the receive and transmit buffer descriptors for the QMC protocol ...
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... Freescale Semiconductor, Inc. Table 5-1. Receive Buffer Descriptor (RxBD) Field Descriptions (Continued) Field Name 1 — — Wrap (final buffer descriptor in table) 0 This is not the last buffer descriptor in the RxBD table. 1 This is the last buffer descriptor in the RxBD table. After this buffer is used, the CPM receives incoming data into the fi ...
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... Freescale Semiconductor, Inc. Table 5-1. Receive Buffer Descriptor (RxBD) Field Descriptions (Continued) Field Name non-octet-aligned frame (HDLC mode only)—A frame that contained a number of bits not exactly divisible by eight was received for any type of nonalignment regardless of frame length. The shortest frame that can be detected is of type Flag-Bit-Flag. This causes the buffer to be closed with the NO error indicated ...
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... Freescale Semiconductor, Inc. ADDRESS XX0 ADDRESS XX4 ADDRESS XX8 ADDRESS X12 ADDRESS XX0 ADDRESS XX4 ADDRESS XX8 ADDRESS X12 — — — XTRA Figure 5-2. Nonoctet Alignment Data In the bottom case, two more bits are received. The frame length is now 13 bytes, and the address positions X13 through X15 point to invalid data ...
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... Freescale Semiconductor, Inc. 5.2 Transmit Buffer Descriptor Figure 5-3 shows the transmit buffer descriptor OFFSET + 0 R — OFFSET + 2 OFFSET + 4 OFFSET + 6 Notes: Entries in boldface must be initialized by the user. For the 68360, the bit numbering is reversed. See Appendix A for more information. Figure 5-3. Transmit Buffer Descriptor (TxBD) Table 5-2 describes the individual fi ...
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... Freescale Semiconductor, Inc. Table 5-2. Transmit Buffer Descriptor (TxBD) Field Descriptions (Continued) Field Name 6 CM Continuous mode 0 Normal operation. 1 The R bit is not cleared by the CPM after this buffer descriptor is closed, allowing the associated data buffer to be retransmitted automatically when the CPM next accesses this buffer descriptor ...
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... Freescale Semiconductor, Inc. 5.3 Placement of Buffer Descriptors The internal dual-ported RAM is used to store the buffer descriptors for all non-QMC operation. This solution causes minimum loading of the external bus. When starting any operation or switching between buffers during operations, several accesses must be made by the CPM to fi ...
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... Freescale Semiconductor, Inc. DPRBASE 2 Kbytes Dual-ported RAM DPRBASE + 0x0c00 SCC1 Parameter RAM 192 Bytes DPRBASE + 0x0d00 SCC2 Parameter RAM 192 Bytes DPRBASE + 0x0e00 SCC3 Parameter RAM 192 Bytes DPRBASE + 0x0f00 SCC4 Parameter RAM 192 Bytes DPRBASE+0x1000 4 Kbytes Internal Registers Figure 5-5. MC68MH360 Internal Memory ...
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... Freescale Semiconductor, Inc. The gaps shown between RAM pages are not implemented on the MC68360MH and cannot be addressed. Table 5-3 shows functions available for various protocols on each SCC for the MC68360. Table 5-3. MC68360 Functions Available Function Transparent HDLC Available? SCC1 Yes ...
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... Freescale Semiconductor, Inc. Transparent DPRBASE + C00 DPRBASE + C00 Transparent Regs = 56 Bytes DPRBASE + C37 DPRBASE + C38 DPRBASE + C5B DPRBASE + C5C Free Area = 120 Bytes DPRBASE + CAF DPRBASE + CAF DPRBASE + CB0 DPRBASE + CB0 Misc Regs = 16 Bytes DPRBASE + CBF DPRBASE + CBF Ethernet DPRBASE + C00 ...
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... Freescale Semiconductor, Inc. Transparent DPRBASE + D00 DPRBASE + D00 Transparent Regs = 56 Bytes DPRBASE + D37 DPRBASE + D38 DPRBASE + D5B DPRBASE + D5C Free Area = 72Bytes DPRBASE + DAF DPRBASE + DAF DPRBASE + D80 DPRBASE + D80 SPI Regs = 40Bytes DPRBASE + DA7 DPRBASE + DA7 DPRBASE + DA8 Free Area ...
Page 82
... Freescale Semiconductor, Inc. Transparent DPRBASE+E00 DPRBASE+E00 Transparent Regs = 56 Bytes DPRBASE+E37 DPRBASE+E38 Free Area DPRBASE+E5B = 56 Bytes DPRBASE+E5C DPRBASE+E6F DPRBASE+E6F DPRBASE+E70 DPRBASE+E70 IDMA1 Regs DPRBASE+E7B DPRBASE+E7B = 12 Bytes DPRBASE+E7C DPRBASE+E7C Free Area DPRBASE+E7F DPRBASE+E7F = 4Bytes DPRBASE+E80 DPRBASE+E80 SMC1 Regs = 56 Bytes DPRBASE+EB7 DPRBASE+EB7 DPRBASE+EB8 DPRBASE+EB8 ...
Page 83
... Freescale Semiconductor, Inc. Transparent DPRBASE + F00 DPRBASE + F00 Transparent Regs = 56 Bytes DPRBASE + F37 DPRBASE + F38 Free Area DPRBASE + F5B = 56 Bytes DPRBASE + F5C DPRBASE + F6F DPRBASE + F6F DPRBASE + F70 DPRBASE + F70 IDMA2Regs DPRBASE + F7B DPRBASE + F7B = 12 Bytes DPRBASE + F7C DPRBASE + F7C Free Area ...
Page 84
... Freescale Semiconductor, Inc. 5.3.3 MPC860MH Internal Memory Structure Figure 5-11 shows the internal memory structure of the MPC860MH. To support 32 channels on the MP860, only 2-Kbyte dual-ported RAM is needed for channel-specific parameters. Each logical channel occupies 64 bytes; thus 32 channels require 2 Kbytes, leaving 2 Kbytes free in the dual-ported RAM for buffer descriptors for other protocols. ...
Page 85
... Freescale Semiconductor, Inc. If the QMC operates with a full 64 channels, no space is left in the lower 4-Kbyte area. In this case, the only free areas are in the RAM pages, each 256-bytes large. Depending on the functions, channels and protocols used, some areas remain free for buffer descriptors. Also particular function is not enabled, its parameter RAM area may also be used ...
Page 86
... Freescale Semiconductor, Inc. Transparent IMMR + 3C00 IMMR+3C00 Transparent Regs = 56 Bytes IMMR + 3C37 IMMR + 3C5B IMMR + 3C38 IMMR + 3C5C Free Area = 72Bytes IMMR + 3C7F IMMR + 3C7F IMMR + 3C80 IMMR + 3C80 Regs = 48Bytes IMMR + 3CAF IMMR + 3CAF IMMR + 3CB0 IMMR + 3CB0 Misc Regs ...
Page 87
... Freescale Semiconductor, Inc. Transparent IMMR + 3D00 IMMR + 3D00 Transparent Regs = 56 Bytes IMMR + 3D37 IMMR + 3D5B IMMR + 3D38 IMMR + 3D5C Free Area = 72Bytes IMMR + 3D7F IMMR + 3D7F IMMR + 3D80 IMMR + 3D80 SPI Regs = 48Bytes IMMR + 3DAF IMMR + 3DAF IMMR + 3DB0 IMMR + 3DB0 ...
Page 88
... Freescale Semiconductor, Inc. Transparent IMMR + 3E00 IMMR + 3E00 Transparent Regs = 56 Bytes IMMR + 3E37 IMMR + 3E5B IMMR + 3E38 IMMR + 3E5C Free Area = 72Bytes IMMR + 3E7F IMMR + 3E7F IMMR + 3E80 IMMR + 3E80 SMC1 Regs = 56 Bytes IMMR + 3EB7 IMMR + 3EB7 IMMR + 3EB8 IMMR + 3EB8 ...
Page 89
... Freescale Semiconductor, Inc. Transparent IMMR + 3F00 IMMR + 3F00 Transparent Regs = 56 Bytes IMMR + 3F37 IMMR + 3F5B IMMR + 3F38 IMMR + 3F5C Free Area = 72Bytes IMMR + 3F7F IMMR + 3F7F IMMR + 3F80 IMMR + 3F80 SMC2 Regs = 56 Bytes IMMR + 3FB7 IMMR + 3FB7 IMMR + 3FB8 IMMR + 3FB8 ...
Page 90
... Freescale Semiconductor, Inc. 5.3.4 MC68MH360 Configured for QMC and Ethernet Certain difficulties may arise when QMC and Ethernet are used together 25-MHz system, Ethernet can work together with 16 QMC channels. In this case, a careful use of logical channels can free a 1-Kbyte space in the parameter area for up to 128 buffer descriptors. For more information, see Section 5.3.2, “ ...
Page 91
... Freescale Semiconductor, Inc. Chapter 6 QMC Initialization 60 60 This section describes the essential steps to initialize QMC after a hard reset. Section 6.1, “Initialization Steps,” discusses the steps required to initialize the QMC protocol, and Section 6.2, “68MH360 T1 Example,” provides example code. 6.1 Initialization Steps This section describes the steps required to initialize the QMC protocol ...
Page 92
... Freescale Semiconductor, Inc. Since the SIMODE register defaults to 0x0000_0000, a typical application may set these bits as follows: SIMODE.CRTa = 1; SIMODE.RFSDa = 1; SIMODE.TFSDa = 1; Step 2: Initialize the SICR (SI clock route) register. The SICR register is defined on page 7-86 of the MC68360 User’s Manual and page 16-121 of the MPC860 User’s Manual. ...
Page 93
... Freescale Semiconductor, Inc. Step 5: Configure port C for TDMa and/or TDMb signals L1ST1 and/or 4; L1TSYNCx and/or L1RSYNCx. For more information on port C, see page 7-365 of the MC68360 User’s Manual and page 16-465 of the MPC860 User’s Manual. The following setting enables L1RSYNCx, L1TSYNCx, and all L1STx strobes. Note that if common clocking is used, selected by the CRTx bit in the SI MODE register, only L1RSYNCx is required ...
Page 94
... Freescale Semiconductor, Inc. Step 7: Enable TDM. The TDMs are enabled via the SI global mode register, SIGMR. For more information on SIGMR programming, see page 7-77 of the MC68360 User’s Manual and page 16-113 of the MPC860 User’s Manual. See Table 6-3 for SIGMR bit settings. ...
Page 95
... Freescale Semiconductor, Inc. Table 6-4. GSMR_H Bit Settings (Continued) Name No. of Bits CDS 1 CD sampling CTSS 1 CTS sampling TFL 1 Transmit FIFO length RFW 1 Receive FIFO width TXSY 1 Transmitter synchronized to the receiver SYNL 2 Sync length RTSM 1 RTS mode RSYN 1 Receive synchronization timing A typical setting would be: GSMR_H = 0x0000_0780 ...
Page 96
... Freescale Semiconductor, Inc. Clear the ENR and ENT bits at the end of the initialization. The MODE setting for QMC mode is 0b1010. A typical setting would be: GSMR_L = 0x0000_000A; Step 11. Initialize basic global multichannel parameters as follows. See Chapter 2, “QMC Memory Organization,” for more information. ...
Page 97
... Freescale Semiconductor, Inc. Step 13. Initialize the time slot assignment tables, TSATTx and TSATRx. Each valid entry should have the V bit set. Clear the W bit in all entries except the last entry in the table. The ‘mask’ bits determine which bits of the time slot are processed by the CPM–normally set to 0xFF to process all 8 bits. The 6-bit CP fi ...
Page 98
... Freescale Semiconductor, Inc. Step 16. Initialize channel-specific parameters for HDLC or transparent mode as follows. For more information on HDLC, see Section 2.4.1, “Channel-Specific HDLC Parameters,” and for transparent mode, see Section 2.4.2, “Channel-Specific Transparent Parameters.” Repeat for each of the enabled channels. ...
Page 99
... Freescale Semiconductor, Inc. • MFLR/MRBLR: MFLR (HDLC mode)—application-dependent. MRBLR (transparent mode)—must be divisible by 4 and large (>30) for better performance. ch[x].MFLR = 60; • TRNSYNC: transparent synchronization, system-specific. Step 17. Initialize RxBDs. Prepare an adequate number of receive buffers at the location addressed by RBASE. In the status word, set the E bit, set the I bit if interrupts are required and set the W bit for the last buffer descriptor. The data length is normally cleared, and the buffer pointer is set to a location in external memory. See Section 5.1, “ ...
Page 100
... Freescale Semiconductor, Inc. Note the ENT bit is initially cleared, but then must be set when the channel is ready to start transmitting. Similarly, the POL bit is initially cleared, but then must be set each time a buffer descriptor is enabled to transmit. Example settings are as follows: ch[x].CHAMR.MODE = 1; ...
Page 101
... Freescale Semiconductor, Inc. struct descs { rxbdq recvbd0; txbdq xmitbd0; } chbd[4]; static char *poem[6]; short linecntr; struct intrpten { unsigned V:1; unsigned W:1; unsigned NID:1; unsigned IDL:1; unsigned :1; unsigned CHNMBR:5; unsigned MRF:1; unsigned UN:1; unsigned RXF:1; unsigned BSY:1; unsigned TXB:1; unsigned RXB:1; } intrpt[10]; ...
Page 102
... Freescale Semiconductor, Inc. pvec = (int *) (getvbr() + (((vecblk << 0x1E) * 4));/* vector address */ *pvec = (int) SCC1esr; pdpr->TRR4 = 8; pdpr->TMR4. pdpr->TMR4. pdpr->TMR4.FRR = 1; pdpr->TMR4.ICLK = 1; pdpr->TGCR.RST4 = 1; pdpr->PAPAR |= 0x8000 pdpr->PADIR |= 0x8000; pdpr->TRR3 = 174; pdpr->TMR3. pdpr->TMR3. pdpr->TMR3.FRR = 1; ...
Page 103
... Freescale Semiconductor, Inc. pdpr->GSMR_H1.CDP = 1; pdpr->GSMR_H1.CTSP = 1; pdpr->GSMR_H1.CDS = 1; pdpr->GSMR_H1.CTSS = 1; /* GSMR_H1 is zero from reset */ pdpr->GSMR_L1.MODE = 0xA; /* GSMR_L1 is zero from reset */ pdpr->SCC1.MCBASE = 0x1_0000 base located 0x1_0000 */ pdpr->SCC1.INTBASE = 0xF000; pdpr->SCC1.MRBLR = 60; pdpr->SCC1.GRFTHR = 1; pdpr->SCC1.GRFCNT = 1; pdpr->SCC1.C_MASK32 = 0xDEBB20E3;/* init 32-bit CRC const */ pdpr-> ...
Page 104
... Freescale Semiconductor, Inc. pdpr->ch[v1].ZDSTATE = 0x80; pdpr->ch[v1].INTMSK = 0xA; pdpr->ch[v1].MFLR = 60; pdpr->ch[v1].TBPTR = pdpr->ch[v1].TBASE; pdpr->ch[v1].RBPTR = pdpr->ch[v1].RBASE; }; chbd[0].recvbd0.rxbdptr = (char *)((int)chbd + 0x100);/* pointer=0x100 */ chbd[1].recvbd0.rxbdptr = (char *)((int)chbd + 0x200);/* pointer=0x200 */ chbd[2].recvbd0.rxbdptr = (char *)((int)chbd + 0x300);/* pointer=0x300 */ chbd[3].recvbd0.rxbdptr = (char *)((int)chbd + 0x400) ...
Page 105
... Freescale Semiconductor, Inc. poem[3] = "Couldn't put Humpty together again\n\r"; poem[4] = ""; poem[5] = ""; linecntr = 0; for (linecntr = 0; linecntr < 4; linecntr++) { chbd[linecntr].xmitbd0.txbdptr = poem[linecntr];/* pointer */ chbd[linecntr].xmitbd0.txbdcnt = strlen(poem[linecntr]) + 1;/* init xmit cnt */ chbd[linecntr].xmitbd0.txbdsac.R = 1;/* set xmit for ( < 3; v1++) { pdpr->ch[v1].CHAMR.MODE = 1; pdpr->ch[v1].CHAMR.IDLM = 0; ...
Page 106
... Freescale Semiconductor, Inc. {}; if ((er & {}; if ((er & {}; if ((er & {}; pdpr->CISR = 0x4000_0000; } getmbar() { asm(" move.w #7,d0"); asm(" movec.l d0,sfc"); asm(" lea.l $3ff00,a0"); asm(" moves.l (a0),d0"); } getvbr() { asm(" movec.l vbr,d0"); } inittsatr(maxts) short maxts; { short curts; for (curts = 0; curts < maxts; curts++) { pdpr-> ...
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... Freescale Semiconductor, Inc. 6.3 Restarting the Transmitter A global underrun may require the SCC transmitter to be restarted. However, for channel- specific errors, only the affected channel need be restarted. The following steps are required to restart each channel: • Prepare buffer descriptors. • Set the POL bit in the channel mode register. ...
Page 108
... Freescale Semiconductor, Inc. Table 6-7. Pointer Registers Offset Name Channel-specifi internal data pointer parameters— internal byte count HDLC and transparent 28 Rx internal data pointer 2E Rx internal byte count 6.6.2 State Registers The QMC has two sets of state parameters—global and channel-specific. These registers change if the QMC is running and the SCC is receiving clock ...
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... Freescale Semiconductor, Inc. Chapter 7 Features Deleted in MC68MH360 MC68MH360 operating in normal mode without the QMC protocol can perform the same functions as the MC68360 and MC68EN360 with two exceptions in protocol support. In order to create space in the CPM ROM for the QMC protocol, the support for Centronics and BiSync have been removed from the MH360 ...
Page 110
... Freescale Semiconductor, Inc. QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
Page 111
... Freescale Semiconductor, Inc. Chapter 8 Performance 80 80 Calculating performance is key to choosing the clock frequency required for a given system. For the 860MH and MH360, the large number of possible channel combinations complicates performance estimation. This chapter addresses the problem by first providing a performance table for common confi ...
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... Freescale Semiconductor, Inc. Table 8-1. Common QMC Configurations (Continued) Protocols Selected SCC1: 10-Mbps Ethernet; SCC2 64-Kbps QMC; SCC3 64-Kbps QMC; SCC4: 64-Kbps HDLC. TDM bit rate = 2.048 Mbps SCC1: 10-Mbps Ethernet; SCC2 64-Kbps QMC; SCC3 64-Kbps QMC; SCC4: 64-Kbps HDLC. TDM bit rate = 1.544 Mbps SCC1: 24-channel QMC ...
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... Freescale Semiconductor, Inc. Table 8-2. CPM Performance Table (Continued) SCC Rate: Clock Frequency Protocol Mbps: MHz Ethernet 1 : 1.136 HD SMC transparent 1 : 16.67 FD SMC UART 1 : 113.636 FD QMC 1 : 11.90 FD Bisync 1: 16. Full duplex Half duplex Further examples are given in Appendix A of the MPC860 user’s manual. ...
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... Freescale Semiconductor, Inc. Example #1 A device is operating at 25 MHz. SCC1 runs 1x10-Mbps Ethernet in half duplex, SCC2 runs 1 x 2-Mbps HDLC, SCC3 runs 1 x 64-Kbps HDLC, SCC4 runs 1 x 9.6-Kbps UART and SMC1 runs 1 x 38-Kbps SMC UART. The following equation applies: ...
Page 115
... Freescale Semiconductor, Inc. 8.3 Bus Latency and Peak Load Each time slot is 8 bits, but the QMC protocol transfers 32 bits of data whenever possible. Thus, for each active channel operating within large frames, two 32-bit SDMA data transfers (one for Tx and one for Rx) occur approximately every fourth TDM frame (every 500 s in CEPT/T1 interfaces) ...
Page 116
... Freescale Semiconductor, Inc. In the worst-case scenario, all channels open and close a buffer during the same TDM frame resulting in the peak load all performance calculations are based on. This peak load is far from the norm and can be controlled by the transmitter spreading the starting point of transmit buffers over several TDM frames ...
Page 117
... Freescale Semiconductor, Inc. Chapter 9 Multi-Subchannel (MSC) Microcode 90 90 The RISC processor in the PowerQUICC has an option to execute microcode from the internal dual-ported RAM. Motorola uses this feature to enhance existing protocols or implement additional protocols. Customers can purchase RAM microcodes in an object- code format and download it to the PowerQUICC dual-ported RAM during system initialization ...
Page 118
... Freescale Semiconductor, Inc. 9.2 MSC Microcode Operation In normal operation (without the MSC microcode), the QMC protocol allows specific bits in an 8-bit time slot to be masked to create a single subchannel per SCC. A problem arises when multiple subchannels are multiplexed within a single time slot as in GSM (global system for mobile communications) where four 16-Kbps subchannels are multiplexed into a single 64-Kbps channel over a 2 ...
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... Freescale Semiconductor, Inc. As the L bit (bit time slot assignment table entry) is taken from the original channel pointer field, the addressing capability of the QMC is reduced from 6 bits (64 channels bits (32 channels) for receive and transmit. TS0 TS1 SCC1 LC2A LC2B Masking performed by a single SCC to create four 2-bit channels Figure 9-2 ...
Page 120
... Freescale Semiconductor, Inc. Time Slot Mask(0:1) Time Slot Mask(0: Mask(0: Mask(0: Mask(0:1) Time Slot Mask(0:1) Time Slot Mask(0:1) Figure 9-3. Time Slot Assignment Table Showing MSC Configuration Table 9-1 describes the fields in the time slot assignment table for receive (TSATRx) when the MSC microcode is enabled ...
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... Freescale Semiconductor, Inc. Table 9-1. Time Slot Assignment Table Entry Fields for Receive (MSC) (Continued) Field L Last bit—Identifies the last subchannel in a time slot. 0 This is not the last subchannel in the time slot. 1 This is the last sub channel within an 8-bit time slot.The RISC processor handles the next time slot transferred from the TSA in the next request ...
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... Freescale Semiconductor, Inc. 9.4 MSC Subchanneling Example Figure 9-4 shows an example for eight 20-bit subchannels. Time Slot Time Slot Figure 9-4. Example for Eight 2-Bit Subchannels The example in Figure 9-4 uses two time slots to handle eight 2-bit subchannels. Time slot 0 is subdivided into four 2-bit subchannels. Note that time slot 0 is processed four times for the channels labeled 0A, 0B, 0C and 0D, each with different masks ...
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... Freescale Semiconductor, Inc. 9.5 QMC Memory Organization Figure 9-5 shows the internal memory map of the MPC860MH when the MSC microcode is resident. Note that the microcode resides in the first 1 Kbyte of dual-ported RAM and uses the last 256 bytes of dual-ported RAM for data. This means that the channel-specific parameters are offset from IMMR + 0x2400, and may occupy up to IMMR + 0x2BFF ...
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... Freescale Semiconductor, Inc. 9.6 Multi-Subchannel Initialization The initialization of the MSC microcode is the same as the standard QMC initialization with the following additions: • Prepare TSATTx and TSATRx to include the L (last) bit • The RISC controller trap registers for the MPC860 rev A must be set as follows: — ...
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... Freescale Semiconductor, Inc. Appendix A 68360 Bit Numbering A0 A0 This appendix shows the bit numbering for the 68360. A.1 Time Slot Assignment Table Figure A-1 shows the 68360 bit numbering for a general time slot assignment table for thirty-two 16-bit time slots. The fields will be used to either transmit or receive channels. ...
Page 126
... Freescale Semiconductor, Inc. Figure A-2 shows the 68360 bit numbering for a time slot assignment table for 64-channel common Rx and Tx mapping. Time Slot Mask(7:6) Time Slot Mask(7: Mask(7: Mask(7: Mask(7:6) Time Slot Mask(7:6) Time Slot Mask(7:6) Figure A-2. Time Slot Assignment Table for 64-Channel Common Rx and Tx For More Information On This Product, Go to: www ...
Page 127
... Freescale Semiconductor, Inc. A.2 Registers in HDLC Mode Figure A-3 to Figure A-6 show the 68360 bit numbering for registers in HDLC mode MODE 0 IDLM ENT RESERVED RESET Figure A-3. CHAMR—Channel Mode Register (HDLC) Interrupt Table Entry NID IDL — CHANNEL NUMBER RESET: ...
Page 128
... Freescale Semiconductor, Inc. A.3 Registers in Transparent Mode Figure A-7 to Figure A-10 show the 68360 bit numbering for registers in transparent mode MODE RD 1 ENT RESVD SYNC – RESET: MODCK MODCK Figure A-7. CHAMR—Channel Mode Register (Transparent Mode) INTMSK RESERVED RESERVED RESERVED ...
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... Freescale Semiconductor, Inc. A.5 SCC Event Register Figure A-12 shows the 68360 bit numbering for the Figure A-12. SCC Event (SCCE) Register A.6 SCCM Register Figure A-13 shows the 68360 bit numbering for the SCCM register Figure A-13. SCCM Register A.7 Receive and Transmit Buffer Descriptors Figure A-14 and Figure A-15 show the 68360 bit numbering for the receive and transmit buffer descriptors ...
Page 130
... Freescale Semiconductor, Inc. QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
Page 131
... Freescale Semiconductor, Inc. Appendix B Frequently-Asked Questions B0 B0 This appendix provides a list of frequently-asked questions and solutions for the MH360 and 860MH. B.1 Questions Common to MH360 and 860MH Q: What are the performance differences between the 68MH360 and 860MH? A: Since the 860 and 360 have the same CPM, performance scales linearly with frequency as shown in Table B-1 ...
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... Freescale Semiconductor, Inc. Therefore, a 50-MHz MPC860MH will be needed to run 64 channels of HDLC on one device. B.2 860MH-Related Questions Q: Is Ethernet only available on SCC1 for both 860EN and 860MH? A: Ethernet is available on any channel. We recommend it on SCC1 due to its larger FIFO. Q: How is 64-channel QMC implemented on the 50-MHz 860MH? What is the serial speed of the TDM channels? A: Use two SCCs running 32-channel QMC protocol ...
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... Freescale Semiconductor, Inc. • A hybrid approach runs a single line multiplexed time slots to two separate SCCs, each with its own set of parameters. Normally this would route 32 time slots to each SCC. This would have the benefit of doubling your effective FIFO depth, allowing greater system design flexibility. ...
Page 134
... Freescale Semiconductor, Inc. B.3 MH360-Related Questions Q: Does the MH360 still have a full Ethernet controller? A: Yes. Q: What frequency MH360 is required to support 10-Mbps Ethernet and 64-channel QMC on a 2.048-Mbps TDM 33-MHz MH360 is required. Q: How should an MH360 be configured to run both 2.048-Mbps QMC and 10-Mbps Ethernet? A: Put Ethernet on SCC1 and split the TDM time slot— ...
Page 135
... Freescale Semiconductor, Inc. transmit time slot 1, but virtual channel 5 could be assigned to receive time slot 1. Therefore, global loopback would cause the data transmitted on channel received on channel 5. • For loopback on an individual time slot, set bit 15 of the corresponding entry in the SIRAM. For the last two methods, use a common transmit/receive clock and transmit/receive sync pulses ...
Page 136
... Freescale Semiconductor, Inc. QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
Page 137
... Freescale Semiconductor, Inc. Appendix C Connecting ISDN Multiple S Interfaces to QUICC32 C0 C0 Using IDL or GCI protocols, the MC145574 (S/T interface) and the MC145572 (U interface) can be gluelessly interfaced to members of the MC68302 family for low-cost, active-ISDN basic rate terminal applications. For applications needing to support more than one basic rate interface (BRI), such as LAN/ WAN bridges, PBX, line cards or multiple-line terminal adaptors, a system solution using multiple MC145574s or MC145572s can be built around a QUICC32 (MC68MH360) ...
Page 138
... Freescale Semiconductor, Inc. Using on-chip time slot assigners, the S/T and U interfaces in IDL2 mode can match the QMC bus structure—both interfaces can be connected to a 2.048-MHz IDL2 bus and route the B1 channel, B2 channel and D channel to any time slot. Figure C-1 shows the IDL2 bus configured to match the QMC protocol. ...
Page 139
... Freescale Semiconductor, Inc. L1CLKx L1TXDx L1RXDx L1SYNC IRQ GPI/O SPICLK SPITX SPIRX QUICC32 Figure C-2. IDL and SCP Connections between the QUICC32 and the S/T Interface The QUICC32 is always a slave on the IDL bus, with the data clock (DCL) and frame sync (FSC) signals acting as inputs. As explained in Section C.3, “ ...
Page 140
... Freescale Semiconductor, Inc. L1CLKx L1TXDx L1RXDx L1SYNC IRQ GPI/O SPICLK SPITX SPIRX QUICC32 Figure C-3. IDL and SCP Connections between the QUICC32 and the U Interface As with the S/T interface example, the U interface must be configured in slave mode with the DCL and FSC signals provided to both the QUICC32 and the U interface. ...
Page 141
... Freescale Semiconductor, Inc. However, this configuration works only if the single master S interface is guaranteed to be active, constantly generating synchronized DCL and FSC signals for the network. Since the designated master transceiver cannot be guaranteed active, all transceivers must be configured in slave mode, and the problem of synchronization remains. ...
Page 142
... Freescale Semiconductor, Inc 2.048-MHz CLK Q Clock Flip-flop 1 Figure C-4. FSC Generation from a 2.048-MHz Clock—Block 8-KHz Clock 2.048-MHz Clock 2.048-MHz Inverted Clock Q Flip-fl Flip-flop 2 FSC Figure C-5. FSC Generation from a 2.048-MHz Clock—Timing The S/T interface includes elastic buffers allowing continued operation under any phase relationship between the IDL frame sync and the network ...
Page 143
... Freescale Semiconductor, Inc. RAM ROM SCP FLASH I/O SPI Management SCC1 Port SCC2 QUICC32 IDL2 TSA SCC3 33 MHz BRG4 I/O INT SEL DIVIDER by 256 (FRAME SYNC GENERATOR) Figure C-6. Connection between Four S/T Interfaces and the QUICC32 Appendix C. Connecting ISDN Multiple S Interfaces to QUICC32 For More Information On This Product, Go to: www ...
Page 144
... Freescale Semiconductor, Inc. C.3.1.1 Activation Procedure If no S/T transceiver is active, no TCLK clock is generated. Once the first transceiver is activated, it will generate a TCLK signal only if DCL and FSC signals are present as well. Pseudo DCL and FSC signals generated from one of the baud rate generators (BRG) of the QUICC32 can be used to generate the TCLK signal. The BRG can generate a clock based on the QUICC32’ ...
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... Freescale Semiconductor, Inc TCLK Enabled IRQ3 TX (Rx Info 2) RX IRQ3 (Rx Info 4) Time 1: 1250 to 1500 S/T Frames x 250 ms) 2: > 750 S/T Frames x 250 ms) 3: > 300 ms Figure C-7. Timing Diagram for an Activation Initiated by the NT Appendix C. Connecting ISDN Multiple S Interfaces to QUICC32 For More Information On This Product, Go to: www ...
Page 146
... Freescale Semiconductor, Inc TCLK Enabled IRQ3 TX (Rx Info2) RX IRQ3 (Rx Info 4) Time 1: 500 to 750 S/T Frames x 250 ms 1000 to 1500 S/T Frames x 250 ms) 4: > 1000 S/T Frames x 250 ms) 5: > 300 ms Figure C-8. Timing Diagram for an Activation Initiated by the TE QMC Supplement For More Information On This Product, Go to: www ...
Page 147
... Freescale Semiconductor, Inc. C.3.1.2 Deactivation Procedure When the clock-master S/T interface is deactivated, the QUICC32 receives an interrupt indicating the deactivation status (IRQ3 —register NR3 bit 3— meaning Info 0 of Figure C-9 has been received). Then, if another S/T interface is active, its TCLK signal must be selected to become the clock master ...
Page 148
... Freescale Semiconductor, Inc. C.3.2 MC145572 U Interface The FREQREF signal of the MC145572 provides a clock synchronized to the network timing for the U interface. This frequency reference is a fixed 2.048-MHz clock enabled by setting OR8[4] in the MC145572 register set. The U interface’s FREQREF differs from the TCLK of the S/T interface. When enabled, the FREQREF signal generates the 2 ...
Page 149
... Freescale Semiconductor, Inc. RAM ROM SCP FLASH I/O SPI Management SCC1 Port SCC2 QUICC32 IDL2 TSA SCC3 33 MHz I/O INT SEL DIVIDER by 256 (FRAME SYNC GENERATOR) Figure C-10. Connection between Four U Interfaces and the QUICC32 Appendix C. Connecting ISDN Multiple S Interfaces to QUICC32 For More Information On This Product, Go to: www ...
Page 150
... Freescale Semiconductor, Inc. C.3.2.1 Activation Procedure During the initialization, the FREQREF signal of each U interface is enabled. A multiplexer commanded by the QUICC32 is used to select the U interface clock master. When the first MC145572 is activated, its FREQREF signal synchronizes to the network. The MC145572 then sends an interrupt to the QUICC32 (IRQ1— register NR3[1]— ...
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... Freescale Semiconductor, Inc. C.3.3.2 U-Interface Configuration Do the following for U-interface configuration: • IDL2 with time slot assigner (TSA enabled in reg. OR6[5–7]; TSA selection in reg. OR0 to OR5) • Slave mode (DCL & FSC are input) - (pin M/S to GND) • FREQREF enabled at 2.048 MHz (reg. OR8[ C.3.3.3 QUICC32 Confi ...
Page 152
... Freescale Semiconductor, Inc. QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. A Acronyms and abbreviations, xiii Alignment non-octet alignment data, 5-4 B Bibliography of additional reading, xii Bit numbering, MC68360, A-1 Buffer descriptor buffer descriptor tables, 2-4 data buffer pointer, 2-5 placement, 5-7 RxBD, 5-1 TxBD, 5-5 Bus latency and peak load, 8-5 ...
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... Freescale Semiconductor, Inc. M MC68MH360 ethernet configuration, 5-20 Memory circular interrupt table, external memory, 4-1 internal memory structures MC68MH360, 2-1, 5-7 MPC860MH, 2-1, 5-14 memory organization, 2-1 memory structure, 2-2 QMC memory organization, 9-7 Multichannel parameters and SCC base, 2-3 Multi-subchannel microcode (MSC) ...
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... Freescale Semiconductor, Inc. S SCC base parameters, 2-3 changing QMC routing tables, 1-10 global multichannel parameters, 2-3, 2-5 multiple assignment tables, 2-10 RAM usage over several SCCs, 5-9 Serial interface (SI), 1-4 Serial routing examples, 1-6 SI RAM errors, 1-10 Signals, inverted, 1-5 Synchronization, 1-5 ...
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... Freescale Semiconductor, Inc. INDEX QMC Supplement For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. QMC Memory Organization Features Deleted in MC68MH360 Multi-Subchannel (MSC) Microcode 68360 Bit Numbering Frequently-Asked Questions Connecting ISDN Interfaces to QUICC32 For More Information On This Product, Go to: www.freescale.com Overview 1 2 QMC Commands 3 QMC Exceptions 4 Buffer Descriptors 5 QMC Initialization 6 7 Performance Index ...
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... Freescale Semiconductor, Inc. Overview 1 QMC Memory Organization 2 QMC Commands 3 4 QMC Exceptions Buffer Descriptors 5 6 QMC Initialization 7 Features Deleted in MC68MH360 Performance 8 Multi-Subchannel (MSC) Microcode 9 68360 Bit Numbering A Frequently-Asked Questions B C Connecting ISDN Interfaces to QUICC32 Index IND For More Information On This Product, ...