MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 100

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Note the ENT bit is initially cleared, but then must be set when the channel is ready to start
transmitting. Similarly, the POL bit is initially cleared, but then must be set each time a
buffer descriptor is enabled to transmit. Example settings are as follows:
Step 21. Initialize the SCCE register. From reset, SCCEx will be zero requiring no
initialization. However, if required, it can be cleared by writing a 1 in each of the status bits.
See Section 4.1, “Global Error Events,” for more information.
Step 22. Initialize the mask register, SCCMx. Any interrupts which are not used should be
masked in the SCCM register. SCC interrupts should be enabled using the CIMR register,
if required. The CIMR register is defined on page 7-381 of the MC68360 User’s Manual
and page 16-483 of the MPC860 User’s Manual.
Step 23. Enable the transmitter (ENT bit) and the receiver (ENR bit) in the general SCC
mode register (GSMR).
6.2 68MH360 T1 Example
/* This is an example of transmitting and receiving on four
/* HDLC channels in loopback mode. */
/* Equipment : SBC360 Evaluation Board with QUICC32 */
/* (T1MH.C) */
void *const stdout = 0;
#include <string.h>
#include <stdio.h>
#define qmc1
#include "68360.h"
struct dprbase *pdpr;
ch[x].CHAMR.MODE = 1;
ch[x].CHAMR.IDLM = 0;
ch[x].CHAMR.ENT = 1;
ch[x].CHAMR.CRC = 1;
ch[x].CHAMR.NOF = 7;
ch[x].CHAMR.POL = 1;
SCCE1 = 0xF;
SCCM1 = 0xF;
CIMR.SCC1 = 1;
GSMR_L1.ENR = 1;
GSMR_L1.ENT = 1;
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
QMC Supplement
/* select HDLC */
/* no idles between frames */
/* enable channel xmit */
/* select 32-bit CRC */
/* 7 flags between frames */
/* enable polling by RISC */
/* clear all interrupts */
/* enable all interrupts */
/* SCC1 interrupts enabled */
/* enable receiver */
/* enable transmit */
/* standard output device */
/* string functions */
/* I/O functions */
/* SCC1 is multichannel comm */
/* dual-ported RAM equates */
/* pointer to dual-ported RAM */
*/