MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 10

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure
Number
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
9-1
9-2
9-3
9-4
9-5
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10 RSTATE (Transparent Mode) ........................................................................................ A-4
A-11 Command Register.......................................................................................................... A-4
A-12 SCC Event (SCCE) Register........................................................................................... A-5
A-13 SCCM Register ............................................................................................................... A-5
A-14 Receive Buffer Descriptor (RxBD) ................................................................................ A-5
A-15 Transmit Buffer Descriptor (TxBD) ............................................................................... A-5
C-1
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
C-10 Connection between Four U Interfaces and the QUICC32 ...........................................C-13
MC68MH360 SCC1 Parameter RAM Usage ................................................................ 5-10
MC68MH360 SCC2 Parameter RAM Usage ................................................................ 5-11
MC68MH360 SCC3 Parameter RAM Usage ................................................................ 5-12
MC68MH360 SCC4 Parameter RAM Usage ................................................................ 5-13
MPC860MH Internal Memory ...................................................................................... 5-14
MPC860MH SCC1 Parameter RAM Usage.................................................................. 5-16
MPC860MH SCC2 Parameter RAM Usage.................................................................. 5-17
MPC860MH SCC3 Parameter RAM Usage.................................................................. 5-18
MPC860MH SCC4 Parameter RAM Usage.................................................................. 5-19
Two-Bit Subchannel Implementation without MSC Microcode ..................................... 9-2
Two-Bit Subchannel Implementation with MSC Microcode .......................................... 9-3
Time Slot Assignment Table Showing MSC Configuration ........................................... 9-4
Example for Eight 2-Bit Subchannels.............................................................................. 9-6
MPC860MH Internal Memory Map with MSC Microcode Enabled .............................. 9-7
Time Slot Assignment Table .......................................................................................... A-1
Time Slot Assignment Table for 64-Channel Common Rx and Tx Mapping................ A-2
CHAMR—Channel Mode Register (HDLC) ................................................................. A-3
Interrupt Table Entry and INTMSK (HDLC)................................................................. A-3
TSTATE (HDLC) ........................................................................................................... A-3
RSTATE (HDLC)........................................................................................................... A-3
CHAMR—Channel Mode Register (Transparent Mode)............................................... A-4
INTMSK and Interrupt Table Entry (Transparent Mode) .............................................. A-4
TSTATE (Transparent Mode)......................................................................................... A-4
IDL2 Bus Structure for a Connection to the QMC Bus...................................................C-2
IDL and SCP Connections between the QUICC32 and the S/T Interface.......................C-3
IDL and SCP Connections between the QUICC32 and the U Interface..........................C-4
FSC Generation from a 2.048-MHz Clock—Block Diagram .........................................C-6
FSC Generation from a 2.048-MHz Clock—Timing ......................................................C-6
Connection between Four S/T Interfaces and the QUICC32...........................................C-7
Timing Diagram for an Activation Initiated by the NT...................................................C-9
Timing Diagram for an Activation Initiated by the TE .................................................C-10
Timing Diagram for a Deactivation (Always Initiated by the NT) ...............................C-11
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