MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 107

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

6.3 Restarting the Transmitter
A global underrun may require the SCC transmitter to be restarted. However, for channel-
specific errors, only the affected channel need be restarted. The following steps are required
to restart each channel:
A stopped, but not deactivated channel is started as described above. A deactivated channel
must first have the ZISTATE and TSTATE reinitialized to their correct values, followed by
setting TSATTx[V] and CHAMR[ENT]. Lastly, set CHAMR[POL] if the buffers are ready.
6.4 Restarting the Receiver
A global receiver overrun may require the SCC receiver to be restarted. However, for
channel-specific errors, only the affected channel need be restarted. The following steps are
required to restart each channel:
6.5 Disabling Receiver and Transmitter
A transmit channel can be stopped from sending any more data to the line with the STOP
command described in Section 3.1, “Transmit Commands.” The transmitter will continue
to send IDLEs or FLAGs according to the channel mode register setting. To deactivate a
channel, the V bit has to be cleared in the time slot assignment table and the ENT bit has to
be cleared in the channel mode register.
To stop a channel while receiving, use the STOP command as described in Section 3.2,
“Receive Commands,” then perform a restart as described above.
6.6 Debugging Hints
Note that the following guidelines are subject to change; code should not rely on this
information. The hints are for debugging purposes only.
6.6.1 Pointer Registers
Table 6-7 discusses the debugging hints for pointer registers. See Section 2.4.1, “Channel-
Specific HDLC Parameters,” and See Section 2.4.2, “Channel-Specific Transparent
Parameters,” for more information.
• Prepare buffer descriptors.
• Set the POL bit in the channel mode register.
• Prepare buffer descriptors.
• Initialize the ZDSTATE to either 0x080 (HDLC) or 0x1800_0080 (transparent).
• Initialize the RSTATE to 0x3900_0000 for MH360 and 860MH.
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Chapter 6. QMC Initialization