UDA1384H/N1,518 NXP Semiconductors, UDA1384H/N1,518 Datasheet - Page 19

• Manufacturer Part Number: UDA1384H/N1,518
• Description: IC AUDIO CODER/DECODER 44QFP
• Manufacturer: NXP Semiconductors
• Type: Audio Codecr

Specifications of UDA1384H/N1,518

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 5 / 6
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 98 / 110 (Differential), 98 / 110 (Single-Ended)
• Voltage - Supply, Analog: 2.7 V ~ 3.6 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274756518; UDA1384H-T; UDA1384H-T

Philips Semiconductors
10. I
9397 750 14366
Product data sheet
2
C-bus interface
10.1 General
10.2 Characteristics of the I
10.3 Bit transfer
Table 15:
The UDA1384 has an I
with the I
accessible via pin MCMODE with signal QMUTE.
The exchange of data and control information between the microcontroller and the
UDA1384 is accomplished through a serial hardware interface comprising the following
pins as shown in
The bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to the supply voltage V
stages of a microcontroller. For a 400 kHz IC, the recommendation for this type of bus
from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a
pull-up resistor can be used, between 200 pF and 400 pF a current source or switched
resistor must be used). Data transfer can only be initiated when the bus is not busy.
One data bit is transferred during each clock pulse (see
line must remain stable during the HIGH period of the clock pulse as changes in the data
line at this time will be interpreted as control signals. The maximum clock frequency is
400 kHz.
To be able to run on this high frequency, all the inputs and outputs connected to this bus
must be designed for this high-speed I
Byte
1
2
3
4
5
6
•
•
MCCLK: clock line with signal SCL
MCDATA: data line with signal SDA
L3-bus
mode
address
data
transfer
address
data
transfer
data
transfer
data
transfer
2
C-bus interface protocol. In the I
L3-bus read data
Action
device
address
register
address
device
address
register
address
data
byte 1
data
byte 2
Table
Rev. 02 — 17 January 2005
2
11:
C-bus microcontroller interface. All the features are accessible
First in time
Bit 0
0
1
1
0 or 1
D15
D7
2
C-bus
DD
Bit 1
1
A6
1
A6
D14
D6
via a pull-up resistor when connected to the output
2
C-bus according to the Philips specification.
2
Bit 2
0
A5
0
A5
D13
D5
C-bus mode, the DAC mute function is
Bit 3
1
A4
1
A4
D12
D4
Multichannel audio coder-decoder
Figure
Bit 4
0
A3
0
A3
D11
D3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
13). The data on the SDA
Latest in time
Bit 5
1
A2
1
A2
D10
D2
UDA1384
Bit 6
0
A1
0
A1
D9
D1
Bit 7
0
A0
0
A0
D8
D0
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