UJA1075TW/5V0/WD,1 NXP Semiconductors, UJA1075TW/5V0/WD,1 Datasheet
UJA1075TW/5V0/WD,1
Specifications of UJA1075TW/5V0/WD,1
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UJA1075TW/5V0/WD,1 Summary of contents
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UJA1075 High-speed CAN/LIN core system basis chip Rev. 02 — 27 May 2010 1. General description The UJA1075 core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a high-speed Controller Area ...
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... NXP Semiconductors 2. Features and benefits 2.1 General Contains a full set of CAN and LIN ECU functions: CAN transceiver and LIN transceiver Scalable 3 voltage regulator delivering up to 250 mA for a microcontroller and peripheral circuitry; an external PNP transistor can be connected for better heat distribution over the PCB ...
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... NXP Semiconductors Output signal (WBIAS) to bias the wake pins, selectable sampling time Standby mode with very low standby current and full wake-up capability; V1 active to maintain supply to the microcontroller Sleep mode with very low sleep current and full wake-up capability 2.5 Control and Diagnostic features ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1075TW/5V0/WD HTSSOP32 UJA1075TW/3V3/WD UJA1075TW/5V0 UJA1075TW/3V3 [1] UJA1075TW/5V0xx versions contain regulator (V1); UJA1075TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. 4. Block diagram BAT GND SCK SDI SDO SCSN WAKE1 WAKE WAKE2 WDOFF ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol i.c. i.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCSN TXDC RXDC TEST1 WDOFF LIMP UJA1075_2 Product data sheet i. TXDL 4 V1 RXDL 5 RSTN 6 INTN SDI SDO 10 SCK ...
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... NXP Semiconductors Table 2. Symbol WAKE1 WAKE2 V2 CANH CANL GND SPLIT LIN DLIN i.c. WBIAS VEXCC TEST2 VEXCTRL BAT The exposed die pad at the bottom of the package allows for better heat dissipation from the SBC via the printed circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND ...
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... NXP Semiconductors 6.1 System Controller 6.1.1 Introduction The system controller manages register configuration and controls the internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals. The system controller is a state machine. The SBC operating modes, and how transitions between modes are triggered, are illustrated in more detail in the following sections ...
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... NXP Semiconductors V below BAT power-off threshold V th(det)poff (from all modes) V below BAT power-on threshold V th(det)pon CAN/LIN: Active/Lowpower successful watchdog trigger Fig 3. UJA1075 system controller UJA1075_2 Product data sheet Overtemp V1: OFF V2: OFF limp home = LOW (active) CAN/LIN: Off and high resistance watchdog: OFF ...
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... NXP Semiconductors 6.1.2 Off mode The SBC switches to Off mode from all other modes if the battery supply drops below the power-off detection threshold (V and the bus systems are in a high-resistive state. The CAN bus pins are floating in this mode. As soon as the battery supply rises above the power-on detection threshold (V ...
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... NXP Semiconductors • The chip temperature rises above the OTP activation threshold, T SBC to switch to Overtemp mode 6.1.5 Sleep mode Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the Mode_Control register no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source is enabled (CAN, LIN or WAKE). Any attempt to enter Sleep mode while one of these conditions has not been satisfied will result in a short reset (3.6 ms min. pulse width ...
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... NXP Semiconductors SCS SCK 01 sampled SDI X SDO X floating Fig 4. SPI timing protocol 6.2.2 Register map The first three bits (A2, A1 and A0) of the message header define the register address. The fourth bit (RO) defines the selected register as read/write or read only. Table 3. Address bits 15, 14 and 13 ...
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... NXP Semiconductors 6.2.3 WD_and_Status register Table 4. WD_and_Status register Bit Symbol Access Power-on default 15:13 A2, A1 000 WMC R/W 0 [1] 10:8 NWP R/W 100 7 WOS/SWR R V1S V2S WLS1 WLS2 R - 2:0 reserved R 000 [1] Bit NWP is set to it’s default value (100) after a reset. ...
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... NXP Semiconductors 6.2.4 Mode_Control register Table 5. Mode_Control register Bit Symbol Access Power-on default 15:13 A2, A1 001 12 RO R/W 0 11:10 MC R/W 00 [1] 9 LHWC R/W 1 [2] 8 LHC R ENC R LSC R WBC R PDC R/W 0 3:0 reserved R 0000 [1] Bit LHWC is set to 1 after a reset. [2] Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset. ...
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... NXP Semiconductors 6.2.5 Int_Control register Table 6. Int_Control register Bit Symbol Access Power-on default 15:13 A2, A1 010 V1UIE R V2UIE R STBCL R reserved R 0 7:6 WIC1 R/W 00 5:4 WIC2 R STBCC R/W 0 UJA1075_2 Product data sheet High-speed CAN/LIN core system basis chip Description register address ...
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... NXP Semiconductors Table 6. Int_Control register Bit Symbol Access Power-on default 2 RTHC R WSE1 R WSE2 R/W 0 UJA1075_2 Product data sheet High-speed CAN/LIN core system basis chip Description reset threshold control 0: The reset threshold is set to the undervoltage detection voltage (V ; see Table 10) uvd 1: The reset threshold is set to the undervoltage detection voltage (V ...
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... NXP Semiconductors 6.2.6 Int_Status register [1] Table 7. Int_Status register Bit Symbol Access Power-on default 15:13 A2, A1 011 V1UI R V2UI R LWI R reserved R WI1 R POSI R WI2 R CWI R/W 0 2:0 reserved R 000 [1] An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register. ...
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... NXP Semiconductors 6.4 Watchdog (UJA1075/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see default watchdog period is 128 ms. A watchdog trigger event is any write access to the WD_and_Status register. When the watchdog is triggered, the watchdog timer is reset ...
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... NXP Semiconductors • the SBC is in Standby mode and bit WMC = 0 or • the SBC is in Normal mode and bit WMC = 1 6.4.3 Watchdog Off behavior The watchdog is disabled in this state. The watchdog is in Off mode when: • the SBC is in Off, Overtemp or Sleep modes • ...
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... NXP Semiconductors The reset pulse width (t generated undervoltage event (see (V > V BAT selected by connecting a 900 Ω ±10 % resistor between pins RSTN and V1 resistor is not connected, the reset pulse will be long (see In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short. ...
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... NXP Semiconductors 6.6 Power supplies 6.6.1 Battery pin (BAT) The SBC contains a single supply pin, BAT. An external diode is needed in series to protect the device against negative voltages. The operating range is from 4 The SBC can handle maximum voltages the voltage on pin BAT falls below the power-off detection threshold, V immediately enters Off mode, which means that the voltage regulators and the internal logic are shut down ...
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... NXP Semiconductors current current Fig 7. Figure 7 current of 250 mA with PDC = 0. Any additional load current requirement will be supplied by the PNP transistor its current limit. If the load current continues to rise, I increase above the selected PDC threshold (to a maximum of 250 mA). For a fast ramping load current, V1 will deliver the required load current (to a maximum of 250 mA) until the PNP transistor has switched on ...
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... The thermal performance of the transistor needs to be considered when calculating the value of this resistor. A 3.3 Ω resistor was used with the BCP52-16 (NXP Semiconductors) employed during testing. Note that the selection of the transistor is not critical. In general, any PNP transistor with a current amplification factor (β) of between 60 and 500 can be used ...
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... NXP Semiconductors • the SBC is in Normal mode ( 11) • the transceiver is enabled (bit STBCC = 0; see and • enabled and its output voltage is above its undervoltage threshold • disabled but an external voltage source, or V1, connected to pin V2 is above its undervoltage threshold (see In CAN Active mode, the transceiver can transmit and receive data via the CANH and CANL pins ...
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... NXP Semiconductors 6.7.2 Split circuit Pin SPLIT provides a DC stabilized voltage of 0.5V only. Pin SPLIT is floating in CAN Lowpower and Off modes. The V used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the center tap of the split termination (see A transceiver in the network that is not supplied and that generates a significant leakage current from the bus lines to ground, can result in a recessive bus voltage of < ...
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... NXP Semiconductors 6.8.1 LIN operating modes 6.8.1.1 Active mode The LIN transceiver will be in Active mode when: • the SBC is in Normal mode ( 11) and • the transceiver is enabled (STBCL = 0; see • the battery voltage (V In LIN Active mode, the transceiver can transmit and receive data via the LIN bus pin. ...
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... NXP Semiconductors edge on pin TXDL. If the pin remains LOW for longer than the TXDL dominant time-out time (t to(dom)TXDL The timer is reset by a positive edge on the TXDL pin. 6.9 Local wake-up input The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity ...
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... NXP Semiconductors Fig 12. Typical application for cyclic sampling of wake-up signals 6.10 Interrupt output Pin INTN is an active-LOW, open-drain interrupt output driven LOW when at least one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit in the Int_Status register clears the interrupt status bits and not the pending wake-up. The pending wake-up is cleared on entering Normal mode and when the corresponding standby control bit (STBCC or STBCL ...
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... NXP Semiconductors 7. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V voltage on pin reverse current from R(V1-BAT) pin V1 to pin BAT I current on pin DLIN DLIN V transient voltage trt V electrostatic ESD discharge voltage T virtual junction ...
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... NXP Semiconductors Table 8. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T ambient amb temperature [1] A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (-). [2] Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b. ...
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... NXP Semiconductors 8. Thermal characteristics Fig 13. HTSSOP PCB UJA1075_2 Product data sheet PCB copper area: (bottom layer PCB copper area: (bottom layer measurements: board finish thickness 1.6 mm ±10 %, double-layer Layout conditions for R th(j-a) board, board dimensions 129 mm × 60 mm, board Material FR4, Cu thickness 0.070 mm, thermal via separation 1.2 mm, thermal via diameter 0.3 mm ± ...
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... NXP Semiconductors R (K/W) Fig 14. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper Table 9. Symbol R th(j-a) [1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board. [2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm) and thermal via array under the exposed pad connected to the first inner copper layer ...
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... NXP Semiconductors 9. Static characteristics Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter Supply; pin BAT V battery supply voltage BAT I battery supply current BAT UJA1075_2 ...
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... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter I additional battery supply BAT(add) current V power-on detection th(det)pon threshold voltage V power-off detection th(det)poff threshold voltage ...
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... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter Voltage source; pin V1 V output voltage O R resistance between pin BAT (BAT-V1) and pin V1 ...
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... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter I PNP activation threshold th(act)PNP current I PNP deactivation threshold th(deact)PNP current PNP collector; pin VEXCC ...
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... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter I input leakage current on pin LI(SDI) SDI Serial peripheral interface data output; pin SDO I HIGH-level output current ...
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... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter I pull-down current pd Limp home output; pin LIMP I output current O Wake bias output; pin WBIAS ...
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... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter V differential receiver th(RX)dif threshold voltage V differential receiver hys(RX)dif hysteresis voltage R common-mode input i(cm) resistance Δ ...
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... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter I receiver recessive input BUS_PAS_rec leakage current I receiver dominant input BUS_PAS_dom leakage current including pull-up resistor ...
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... NXP Semiconductors 10. Dynamic characteristics Table 11. Dynamic characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter Voltage source; pin V1 t undervoltage detection d(uvd) delay time t LOW-level clamping det(CL)L detection time Voltage source ...
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... NXP Semiconductors Table 11. Dynamic characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter t delay time from TXDC LOW d(TXDCL-RXDCL) to RXDC LOW t delay time from TXDC to d(TXDC-busdom) bus dominant ...
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... NXP Semiconductors Table 11. Dynamic characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; typical values are given at V specified. Symbol Parameter δ3 duty cycle 3 δ4 duty cycle 4 t rising receiver propagation PD(RX)r delay t falling receiver propagation ...
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... NXP Semiconductors [7] The watchdog will be reset window mode and is triggered at least t watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than t after the start of the watchdog period (watchdog overflows). trig(wd)2 Fig 15. Timing test circuit for CAN transceiver ...
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... NXP Semiconductors Fig 17. Timing test circuit for LIN transceiver V TXDL V BAT LIN bus signal output of receiving V RXDL node A output of receiving V RXDL node B Fig 18. LIN transceiver timing diagram UJA1075_2 Product data sheet RXDL C RXDL TXDL t t bit bit t t bus(dom)(max) bus(rec)(min) ...
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... NXP Semiconductors SCS t SPILEAD SCK SDI X floating SDO Fig 19. SPI timing diagram 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. ...
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... NXP Semiconductors 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad side pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 0.95 mm 1.1 0.25 ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. UJA1075_2 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 14. Revision history Table 14. Revision history Document ID Release date UJA1075_2 20100527 • Modifications: Template upgraded to Rev. 2.11 including revised legal information • Figure • Table • Table • Table • Table I • Table • Section t UJA1075_1 20091125 UJA1075_2 Product data sheet ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: UJA1075_2 Product data sheet High-speed CAN/LIN core system basis chip 15 ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 Power management . . . . . . . . . . . . . . . . . . . . . 2 2.5 Control and Diagnostic features . . . . . . . . . . . . 3 2.6 Voltage regulators Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description ...