UJA1075TW/5V0/WD,1 NXP Semiconductors, UJA1075TW/5V0/WD,1 Datasheet - Page 18

• Manufacturer Part Number: UJA1075TW/5V0/WD,1
• Description: IC SBC CAN/LIN HS 5V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1075TW/5V0/WD,1

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 83µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1075_2
Product data sheet
6.4.3 Watchdog Off behavior
6.5.1 RSTN pin
6.5 System reset
The watchdog is disabled in this state.
The watchdog is in Off mode when:
The following events will cause the SBC to perform a system reset:
A watchdog overflow in Timeout mode requests a cyclic interrupt (CI), if a CI is not already
pending.
The UJA1075 provides three signals for dealing with reset events:
A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t
the microcontroller (external reset). A reset pulse is output on RSTN by the SBC when a
system reset is triggered internally.
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the SBC is in Standby mode and bit WMC = 0 or
the SBC is in Off, Overtemp or Sleep modes
the SBC is in Standby mode and bit WMC = 1
the SBC is in any mode and the WDOFF pin is HIGH
V1 undervoltage (reset pulse length selected via external pull-up resistor on RSTN
pin)
An external reset (RSTN forced LOW)
Watchdog overflow (Window mode)
Watchdog overflow in Timeout mode with cyclic interrupt (CI) pending
Watchdog triggered too early in Window mode
WMC value changed in Normal mode
WDOFF pin state changed
SBC goes to Sleep mode (MC set to 01; see
SBC goes to Sleep mode (MC set to 01; see
STBCC = STBCL = WIC1 = WIC2 = 0
SBC goes to Sleep mode (MC set to 01; see
Software reset (SWR = 1)
SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor
on RSTN pin)
RSTN input/output for performing a global ECU system reset or forcing an external
reset
EN pin, a fail-safe global enable output
LIMP pin, a fail-safe limp home output
the SBC is in Normal mode and bit WMC = 1
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
High-speed CAN/LIN core system basis chip
Table
Table
Table
5) while INTN is driven LOW
5) while
5) while wake-up pending
UJA1075
© NXP B.V. 2010. All rights reserved.
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