UJA1075TW/5V0/WD,1 NXP Semiconductors, UJA1075TW/5V0/WD,1 Datasheet - Page 12

• Manufacturer Part Number: UJA1075TW/5V0/WD,1
• Description: IC SBC CAN/LIN HS 5V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1075TW/5V0/WD,1

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 83µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 4.
[1]
UJA1075_2
Product data sheet
Bit
15:13 A2, A1, A0
12
11
10:8
7
6
5
4
3
2:0
Bit NWP is set to it’s default value (100) after a reset.
Symbol
RO
WMC
NWP
WOS/SWR
V1S
V2S
WLS1
WLS2
reserved
WD_and_Status register
[1]
6.2.3 WD_and_Status register
Access Power-on
R
R/W
R/W
R/W
R/W
R
R
R
R
R
default
000
0
0
100
-
-
-
-
-
000
All information provided in this document is subject to legal disclaimers.
Description
register address
access status
watchdog mode control
nominal watchdog period
watchdog off status/software reset
V1 status
V2 status
wake-up 1 status
wake-up 2 status
0: register set to read/write
1: register set to read only
0: Normal mode: watchdog in Window mode; Standby mode: watchdog in
Timeout mode
1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in
Off mode
000: 8 ms
001: 16 ms
010: 32 ms
011: 64 ms
100: 128 ms
101: 256 ms
110: 1024 ms
111: 4096 ms
0: WDOFF pin LOW; watchdog mode determined by bit WMC
1: watchdog disabled due to HIGH level on pin WDOFF; results in software
reset
0: V1 output voltage above 90 % undervoltage recovery threshold
(V
1: V1 output voltage below 90 % undervoltage detection threshold
(V
0: V2 output voltage above undervoltage release threshold
(V
1: V2 output voltage below undervoltage detection threshold
(V
0: WAKE1 input voltage below switching threshold (V
1: WAKE1 input voltage above switching threshold (V
0: WAKE2 input voltage below switching threshold (V
1: WAKE2 input voltage above switching threshold (V
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uvr
uvd
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Rev. 02 — 27 May 2010
Table
Table
Table
Table
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10)
High-speed CAN/LIN core system basis chip
th(sw)
th(sw)
th(sw)
th(sw)
UJA1075
© NXP B.V. 2010. All rights reserved.
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