UJA1075TW/5V0/WD,1 NXP Semiconductors, UJA1075TW/5V0/WD,1 Datasheet - Page 10

• Manufacturer Part Number: UJA1075TW/5V0/WD,1
• Description: IC SBC CAN/LIN HS 5V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1075TW/5V0/WD,1

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 83µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1075_2
Product data sheet
6.1.5 Sleep mode
6.1.6 Overtemp mode
6.2.1 Introduction
6.2 SPI
Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the
Mode_Control register
no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source
is enabled (CAN, LIN or WAKE). Any attempt to enter Sleep mode while one of these
conditions has not been satisfied will result in a short reset (3.6 ms min. pulse width; see
Section 6.5.1
In Sleep mode, V1 and V2 are off and the bus transceivers will be switched off (Off mode;
STBCC/STBCL = 0; see
STBCC/STBCL = 1) with bus wake-up detection active - see
Section
A CAN, LIN or local wake-up event will cause the SBC to switch from Sleep mode to
Standby mode, generating a (short or long; see
the mode control bits (MC) will be changed to 00 and V1 will be enabled.
The SBC will enter Overtemp mode from Normal mode or Standby mode when the chip
temperature exceeds the overtemperature protection activation threshold, T
In Overtemp mode, the voltage regulators are switched off and the bus systems are in a
high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW
and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW.
The chip temperature must drop a hysteresis level below the overtemperature shutdown
threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the
SBC enters Standby mode and a system reset is generated (reset pulse width of t
long or short; see
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing registers to be read back by the
application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge (see
•
•
•
•
•
The chip temperature rises above the OTP activation threshold, T
SBC to switch to Overtemp mode
SCSN: SPI chip select; active LOW
SCK: SPI clock; default level is LOW due to low-power concept
SDI: SPI data input
SDO: SPI data output; floating when pin SCSN is HIGH
6.8.1). The watchdog is off and the reset pin is LOW.
Figure
and
All information provided in this document is subject to legal disclaimers.
4).
Section 6.5.1
Table
(Table
Rev. 02 — 27 May 2010
11).
Table
5) to 01. The SBC will enter Sleep mode providing there are
6) or in a low-power state (Lowpower mode;
and
Table
High-speed CAN/LIN core system basis chip
11).
Section
6.5.1) system reset. The value of
Section 6.7.1
th(act)otp
UJA1075
© NXP B.V. 2010. All rights reserved.
and
th(act)otp
, causing the
w(rst)
,
10 of 53
,