M25P80-VMW6G STMicroelectronics, M25P80-VMW6G Datasheet - Page 16

• Manufacturer Part Number: M25P80-VMW6G
• Description: M25P80 CMOST7X 2P-3MSO 08 WIDE .208 (EIAJ)
• Manufacturer: STMicroelectronics

Specifications of M25P80-VMW6G

• Lead Free Status / Rohs Status: RoHS Compliant part

M25P80
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b1 and b0 of the Status Reg-
ister. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (WRSR) instruction
is not executed. As soon as Chip Select (S) is driv-
en High, the self-timed Write Status Register cycle
Figure 12. Write Status Register (WRSR) Instruction Sequence
16/41
S
C
D
Q
0
1
High Impedance
2
Instruction
3
Figure
4
5
12..
6
7
MSB
7
8
6
(whose duration is t
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable
Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP2, BP1, BP0) bits, to define the size of
the area that is to be treated as read-only, as de-
fined in
(WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD)
bit in accordance with the Write Protect (W) signal.
The Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not execut-
ed once the Hardware Protected Mode (HPM) is
entered.
9 10 11 12 13 14 15
5
Register In
4
Status
3
Table
2
1
0
2.. The Write Status Register
W
AI02282D
) is initiated. While the Write