M25P80-VMW6G STMicroelectronics, M25P80-VMW6G Datasheet - Page 20

• Manufacturer Part Number: M25P80-VMW6G
• Description: M25P80 CMOST7X 2P-3MSO 08 WIDE .208 (EIAJ)
• Manufacturer: STMicroelectronics

Specifications of M25P80-VMW6G

• Lead Free Status / Rohs Status: RoHS Compliant part

M25P80
Page Program (PP)
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end
of the current page are programmed from the start
address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero).
Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data bytes are guaranteed to be programmed cor-
Figure 15. Page Program (PP) Instruction Sequence
Note: Address bits A23 to A20 are Don’t Care.
20/41
S
C
D
S
C
D
MSB
7
40
0
6
41
1
5
42
Data Byte 2
2
Instruction
4
43 44 45 46 47 48 49 50
3
3
4
2
5
1
Figure
6
0
MSB
7
7
MSB
23
15..
8
6
22 21
9 10
5
Data Byte 3
24-Bit Address
4
51
rectly within the same page. If less than 256 Data
bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
ing any effects on the other bytes of the same
page.
Chip Select (S) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is t
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP2, BP1,
BP0) bits (see
ed.
3
52 53 54 55
3
28 29 30 31 32 33 34 35
2
2
1
1
0
0
MSB
7
MSB
7
Table 3.
6
6
5
Data Byte 1
Data Byte 256
5
4
4
and
3
36 37 38
3
Table
2
2
1
1
0
2.) is not execut-
39
AI04082B
0
PP
)