M25P80-VMW6G STMicroelectronics, M25P80-VMW6G Datasheet - Page 7

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M25P80-VMW6G

Manufacturer Part Number
M25P80-VMW6G
Description
M25P80 CMOST7X 2P-3MSO 08 WIDE .208 (EIAJ)
Manufacturer
STMicroelectronics
Datasheet

Specifications of M25P80-VMW6G

Lead Free Status / Rohs Status
RoHS Compliant part

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SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
Figure 5. Bus Master and Memory Devices on the SPI Bus
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 6. SPI Modes Supported
CPOL
0
1
CPOL=0, CPHA=0
CPOL=1, CPHA=1
SPI Interface with
(CPOL, CPHA) =
CPHA
CS3
(0, 0) or (1, 1)
(ST6, ST7, ST9,
ST10, Others)
0
1
Bus Master
CS2
D
Q
C
C
CS1
MSB
SDO
SDI
SCK
S
SPI Memory
C Q D
Device
W
HOLD
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in
master is in Stand-by mode and not transferring
data:
Figure
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
S
SPI Memory
C Q D
6., is the clock polarity when the bus
Device
W
MSB
HOLD
S
SPI Memory
C Q D
Device
W
AI03746D
HOLD
M25P80
AI01438B
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