M25P80-VMW6G STMicroelectronics, M25P80-VMW6G Datasheet - Page 26

• Manufacturer Part Number: M25P80-VMW6G
• Description: M25P80 CMOST7X 2P-3MSO 08 WIDE .208 (EIAJ)
• Manufacturer: STMicroelectronics

Specifications of M25P80-VMW6G

• Lead Free Status / Rohs Status: RoHS Compliant part

M25P80
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on V
correct value:
–
–
Usually a simple pull-up resistor on Chip Select (S)
can be used to insure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while V
threshold value, V
and the device does not respond to any instruc-
tion.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of t
elapsed after the moment that V
V
the device is not guaranteed if, by this time, V
still below V
26/41
WI
V
delay of t
V
threshold. However, the correct operation of
CC
SS
(min) at Power-up, and then for a further
at Power-down
CC
VSL
(min). No Write Status Register,
WI
– all operations are disabled,
CC
CC
) until V
is less than the POR
CC
CC
rises above the
reaches the
PUW
CC
has
is
Program or Erase instructions should be sent until
the later of:
–
–
These values are specified in
If the delay, t
above V
READ instructions even if the t
fully elapsed.
At Power-up, the device is in the following state:
–
–
Normal precautions must be taken for supply rail
decoupling, to stabilize the V
in a system should have the V
a suitable capacitor close to the package pins.
(Generally, this capacitor is of the order of 0.1µF).
At Power-down, when V
ing voltage, to below the POR threshold value,
V
does not respond to any instruction. (The designer
needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in
progress, some data corruption can result.)
WI
, all operations are disabled and the device
t
t
The device is in the Standby mode (not the
Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
PUW
VSL
CC
afterV
after V
(min), the device can be selected for
VSL
CC
CC
, has elapsed, after V
passed the V
passed the V
CC
drops from the operat-
CC
CC
Table
PUW
CC
feed. Each device
WI
rail decoupled by
(min) level
delay is not yet
threshold
7..
CC
has risen