TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 112

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

14. DMACC0LLI (DMAC Channel0 Linked List Item Register)
[31:2]
[1]
[0]
[Description]
a. <LLI>
Bit
disabled after all DMA transfers associated with it are completed.
The value set to <LLI> must be within 0xFFFF_FFF0.
If the LLI is 0, then the current LLI is the last in the chain, and the DMA channel is
The DMACCxLLI registers have the same structure as DMACC0LLI.
Please refer to the description of DMACC0LLI.
The names and addresses of these registers, please refer to Table 3.8.3.
DMACCxLLI (DMAC Channel x Linked List Item Register) (x = 0 to 7)
LLI
LM
Symbol
Bit
R/W
R/W
Type
TMPA901CM- 111
0x00000000
Undefined
0y0
Reset
Value
Set the start address of the next transfer information
Read as undefined. Write as zero.
AHB master for storing LLI:
0y0: DMA1
0y1: DMA2
Address
Description
(0xF410_0000) + (0x0108)
TMPA901CM
2010-07-29