TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 450

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TMPA901CMXBG

Manufacturer Part Number
TMPA901CMXBG
Description
Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
Manufacturer
Toshiba
Datasheet

Specifications of TMPA901CMXBG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
-
Rom Type
ROMless
Ram (kbytes)
32
Number Of Pins
177
Package
BGA
Vcc
3V
Tft Lcd Controller
Y
Touchscreen Controller
Y
Usb Host Fs With Phy
Y
Usb Device Hs With Phy
Y
Sd Host Controller
-
Cmos Image Sensor Interface
-
I2s
1
Ssp (ch) Spi
1
I2mc/sio (ch)
1
Uart/sio (ch)
2
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
8
10-bit Ad Converter
4
12-bit Da Converter
-
16-bit Timer / Counter
6
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
Y
Low-power Modes
Y
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPA901CMXBG
Manufacturer:
Toshiba
Quantity:
10 000
[31:1]
[0]
Bit
[Description]
timeoutset
timeout_en
a. <timeoutset>
b. <timeouten>
3.
The setting should not be changed during the Master Write transfer. Timeout occurs when
the number of times CLK_U was set is counted after the data of Master Write (Rx)
endpoint is exhausted.
The timeout counter comprises 32 bits of which upper 31 bits can be set by timeoutset
[31:1] of this register, while the lowest bit of the counter is set to 1.
As CLK_U is 30 MHz, approximately 33 [ns] to 143 [s] can be set as a timeout value.
While CLK_U stopped (PHY is being suspended and so on), no timeout interrupt will
occur as the counter does not work.
Used to enable Master Write timeout. It is set to Enable by default.
The setting should not be changed during the Master Write transfer.
0y0: Disable
0y1: Enable
Symbol
Bit
This register is provided for controlling timeout during the Master Write operation.
UDMWTOUT (Master Write Timeout register)
R/W
R/W
Type
0x7FFFFFFF
0y1
TMPA901CM- 449
Reset
Value
Master Write timeout timer setting register
Master Write timeout enable register
0y0: Disable
0y1: Enable
Address = (0xF440_0000) + (0x0008)
Description
TMPA901CM
2010-07-29

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