TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 290

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3. NDFMCR2 (NAND-Flash Control Register 2)
[31:15]
[14:12]
[11]
[10:8]
[7]
[6:4]
[3]
[2:0]
[Description]
Bit
a. <SPLW>, <SPHW>, <SPLR>, <SPHR>
0y111 are prohibited.
These are registers to set the Low and High pulse width of the NDREn and NDWEn pins.
The pulse width is given by the set value the period of HCLK. Setting 0y000, 0y110 and
Symbol
SPLW
SPHW
SPLR
SPHR
Bit
R/W
R/W
R/W
R/W
Type
Undefined
0y000
Undefined
0y000
Undefined
0y000
Undefined
0y000
Reset
Value
TMPA901CM- 289
Read as undefined. Write as zero.
NDWEn Low pulse width setting
Read as undefined. Write as zero.
NDWEn High pulse width setting
Read as undefined. Write as zero.
NDREn Low pulse width setting
Read as undefined. Write as zero.
NDREn High pulse width setting
0y000: Reserved
0y001: 1 cycle of HCLK
0y010: 2 cycles of HCLK
0y011: 3 cycles of HCLK
0y100: 4 cycles of HCLK
0y101: 5 cycles of HCLK
0y110-0y111: Reserved
0y000: Reserved
0y001: 1 cycle of HCLK
0y010: 2 cycles of HCLK
0y011: 3 cycles of HCLK
0y00: 4 cycles of HCLK
0y101: 5 cycles of HCLK
0y110-0y111: Reserved
0y000: Reserved
0y001: 1 cycle of HCLK
0y010: 2 cycles of HCLK
0y011: 3 cycles of HCLK
0y100: 4 cycles of HCLK
0y101: 5 cycles of HCLK
0y110-0y111: Reserved
0y000: Reserved
0y001: 1 cycle of HCLK
0y010: 2 cycles of HCLK
0y011: 3 cycles of HCLK
0y100: 4 cycles of HCLK
0y101: 5 cycles of HCLK
0y110-0y111: Reserved
Description
Address
(0xf201_0000) + (0x0008)
TMPA901CM
2010-07-29