TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 620

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:17]
[16]
[15:14]
[13:12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3:1]
[0]
Bit
8.
WATERMARK
LcdVComp
Reserved
Reserved
Reserved
BGR
LcdDual
LcdMono8
LcdTFT
LcdBW
LcdBpp
LcdEn
LCDControl (LCDC Control Register)
Symbol
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Undefined
0y0
Undefined
0y00
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y000
0y0
Reset
Value
TMPA901CM- 619
Read as undefined. Write as zero.
LCD DMA FIFO watermark level
0y0:Requests DMA when space of 4 words or more occurs in either
0y1:Requests DMA when space of 8 words or more occurs in either
Read as undefined. Write as zero.
Interrupt occurrence timing
0y00: At vertical sync start
0y01: At back porch start
0y10: At display data start
0y11: At front porch start
Write as 1.
Write as 0.
Write as 0.
BGR system selected RGB
0y0: RGB normal output
0y1: BGR red/blue swap
STN panel select
0y0: Single panel LCD
0y1: Dual panel LCD
Selects the monochrome STN LCD parallel bit.
0y0: 4-bit interface for monochrome LCD
0y1: 8-bit interface for monochrome LCD
Selects the panel used for LCD.
0y0: STN panel
0y1: TFT panel
Selects monochrome or color for STN LCD.
0y0: Color
0y1: Monochrome
Number of LCD bits per pixel:
0y000 = 1 bpp
0y001 = 2 bpp
0y010 = 4 bpp
0y011 = 8 bpp
0y100 = 16 bpp
0y101 = Reserved
0y110 = Reserved
0y111 = Reserved
LCD controller enable:
0y0: Disable
0y1: Enable
of the two FIFOs.
of the two FIFOs.
Description
Address
(0xF420_0000) + (0x001C)
TMPA901CM
2010-07-29