TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 420

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

SP0CLK
SP0FSS
SP0DO
SP0DI
Hi-Z(Note1)
Note) The off-chip slave device can tristate the receive line either on the falling edge of SP0CLK after the LSB has
Note1)
Note2)
Hi-Z(Note2)
been latched by the receive shifter, or when the SP0FSS pin goes HIGH.
3) Microwire frame format
message transmission method for half-duplex communications. Each serial
transmission is started by an 8-bit control word, which is sent to the off-chip slave
device. During this transmission, the SSP does not receive input data. After the
message has been transmitted, the off-chip slave decodes it, and after waiting one
serial clock after the last bit of the 8-bit control message has been sent, responds with
the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits. With this configuration, during the idle
period:
falling edge of SP0FSS causes the value stored in the bottom entry of the transmit
FIFO to be transferred to the serial shift register for the transmit logic, and the MSB
of the 8-bit control frame to be shifted out onto the SP0DO pin. SP0FSS remains LOW
and the SP0D1 pin remains tristated during this transmission. The off-chip serial
slave device latches each control bit into its serial shifter on the rising edge of each
SP0CLK. After the last bit is latched by the slave device, the control byte is decoded
during a one clock wait-state, and the slave responds by transmitting data back to the
SSP. Each bit is driven onto SP0DI line on the falling edge of SP0CLK. The SSP in
turn latches each bit on the rising edge of SP0CLK. At the end of the frame, for single
transfers, the SP0FSS signal is pulled HIGH one clock period after the last bit has
been latched in the receive serial shifter, which causes the data to be transferred to the
receive FIFO.
Though the Microwire format is similar to the SPI format, it uses the master/slave
• The SP0CLK signal is forcedly set to LOW.
• SP0FSS is forcedly set to HIGH.
• The transmit data line SP0DO is set to LOW.
A transmission is triggered by writing a control byte to the transmit FIFO. The
Microwire frame format (single transfer)
MSB
When transmission is disable , SP0DO terminal doesn’t output and is high impedance status. This
terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high
impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage
level.
8bit
TMPA901CM- 419
LSB
MSB
Hi-Z(Note1)
4 to 16bit
LSB
TMPA901CM
2010-07-29
Hi-Z(Note2)