TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 631

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Number of colors displayable
simultaneously
Number of available horizontal lines
Number of available vertical lines
Data bus width of transfer destination
Input data
Data type
(LCD driver)
3.18.4
and 8-bit LD data buses are supported.
feature.
To support STN 64-level grayscale mode, VRAM uses the following format. And the external 4-bit
Dummy area
The LCD controller contained in this LSI supports 64-level grayscale LCD display as an optional
Type of LCD panel
D31-D24
LD[７:0] / LD[3:0] pins
LCLAC pin
LCLLP pin
LCLFP pin
LCLCP pin
LCLLE pin
LCD Controller Option Function (LCDCOP)
D23-D18
4
th
pixel
Table 3.18.7 LCDC Optional Feature
64-level grayscale
Max : 640
Max : 480
4/8 bits
LCDC output data in TFT 16-bit mode
Little-endian supported
Data bus dedicated to the LCD driver
AC bias signal (frame signal)
Horizontal sync pulse
Vertical sync pulse
Clock for LCDD data latch (panel clock)
Not used basically
TMPA901CM- 630
D17-D12
3
rd
pixel
STN (Dual/Single)
2
D11-D6
nd
pixel
1
D5-D0
st
TMPA901CM
pixel
2010-07-29