TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 427

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

6.
SSP0IMSC (SSP0 Interrupt mask set and clear register)
[31:4]
[3]
[2]
[1]
[0]
[Description]
a. <TXIM>
b. <RXIM>
c.
d. <RORIM>
Bit
<RTIM>
Enables or disables interrupts that are generated when TxFIFO is half empty or less.
Enables or disables interrupts that are generated when RxFIFO is half full or less.
Enables or disables interrupts that are generated when the data in RxFIFO is not read
out before the timeout period expires.
Enables or disables interrupts that are generated when data is written to RxFIFO while
it is full.
TXIM
RXIM
RTIM
RORIM
Symbol
Bit
R/W
R/W
R/W
R/W
Type
TMPA901CM- 426
Undefined
0y0
0y0
0y0
0y0
Reset
Value
Read as undefined. Write as zero.
Transmit FIFO interrupt enable:
0y0: Disable
0y1: Enable
Receive FIFO interrupt enable:
0y0: Disable
0y1: Enable
Receive timeout interrupt enable:
0y0: Disable
0y1: Enable
Receive overrun interrupt enable:
0y0: Disable
0y1: Enable
Address
Description
(0xF200_2000) + (0x0014)
TMPA901CM
2010-07-29