TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 816

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

1/4 fosch
OFD_RESET
fs
2) Initialization of OFD registers
3) How to confirm the clock fault detection
Reset signal will be asserted after fs clock is
stopped 513 cycles or more at fosch¥DIV4
initialized by an external reset (RESETn pin = Low).
circuit.
The OFD registers (CLKSCR1, CLKSCR2, CLKSCR3, CLKSMN and CLKSMX) are
The OFD registers are also initialized when the PCM mode is exited.
The fault detection can be confirmed by OFD status flag (CLKSCR3<CLKSF>=1) in OFD
Note : A clock fault detection reset is also generated if either of the high-frequency or low-frequency clock
Note: The OFD registers are not initialized by a WDT reset or OFD reset.
Figure 3.26.3
frequency temporarily goes outside the specified range of the frequency ratio due to noise, etc.
Timing of reset generating and releasing (fs clock fault)
TMPA901CM - 815
Reset signal will be resumed after on the fifth
edge of fs clock
TMPA901CM
2010-07-29