SAA-XC866-2FRA 5V BE Infineon Technologies, SAA-XC866-2FRA 5V BE Datasheet
SAA-XC866-2FRA 5V BE
Specifications of SAA-XC866-2FRA 5V BE
SAA-XC866-2FRA BE
SAA-XC866-2FRA5VBEINTR
SAA-XC866-2FRABEINTR
SAA-XC866-2FRABEINTR
SP000281789
Related parts for SAA-XC866-2FRA 5V BE
SAA-XC866-2FRA 5V BE Summary of contents
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... SAA-XC866 8-Bit Single-Chip Microcontroller Data Sheet V1.5 2010- ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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... SAA-XC866 8-Bit Single-Chip Microcontroller Data Sheet V1.5 2010- ...
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... SAA-XC866 Data Sheet Revision History: Previous Version: V1.4 2010-08 Page Subjects (major changes since last revision) Changes from V1.4 2010-08 to V1.5 2010-09 All 3.3 V device variant is added to the data sheet. Parameters specific to the variant are also added. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document ...
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... Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.2.1 Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.2.2 Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.3 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.4 SAA-XC866 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.1 Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.2 Flash Programming Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.1 Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3 ...
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... Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.3.4 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.3.5 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.6 SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.1 Package Parameters (PG-TSSOP-38 108 5.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Data Sheet 3 SAA-XC866 V1.5, 2010-09 ...
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... On-Chip Debug Support 1) or 8K/16K Bytes ROM Boot ROM 8K Bytes XC800 Core XRAM 512 Bytes RAM Timer 0 Timer 1 256 Bytes 16-bit 16-bit Figure 1 SAA-XC866 Functional Units Data Sheet UART SSC Capture/Compare Unit 16-bit Compare Unit 16-bit ADC Timer 2 Watchdog 10-bit 16-bit Timer 8-channel ...
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... Synchronous serial channel (SSC) • On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM • PG-TSSOP-38 pin package • Temperature range T A – SAA (-40 to 140 °C) Data Sheet : 5 SAA-XC866 Summary of Features V1.5, 2010-09 ...
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... The derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the type of delivery For the available ordering codes for the SAA-XC866, please refer to your responsible sales representative or your local distributor. As this document refers to all the derivatives, some descriptions may not apply to a specific product ...
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... SSP V DDC 4/8/16-Kbyte Flash V SSC or 8/16-Kbyte ROM Clock Generator XTAL1 10 MHz XTAL2 On-chip OSC PLL Figure 2 SAA-XC866 Block Diagram Data Sheet Internal Bus XC800 Core T0 & T1 UART CCU6 SSC 2) Timer 2 WDT OCDS 1) Includes 1-Kbyte monitor ROM 2) Includes additional 4-Kbyte Flash 7 SAA-XC866 General Device Information P0 ...
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... Logic Symbol V AREF V AGND RESET MBC TMS XTAL1 XTAL2 Figure 3 SAA-XC866 Logic Symbol Data Sheet General Device Information V V DDP SSP XC866 V V DDC SSC 8 SAA-XC866 Port 0 6-Bit Port 1 5-Bit Port 2 8-Bit Port 3 8-Bit V1.5, 2010-09 ...
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... Pin Configuration P0.3/SCLK_1/COUT63_1 P0.4/MTSR_1/CC62_1 P0.5/MRST_1/EXINT0_0/COUT62_1 P1.6/CCPOS1_1/T12HR_0/EXINT6 P1.7/CCPOS2_1/T13HR_0 P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT/RXDO_1 P0.2/CTRAP_2/TDO_0/TXD_1 P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1 P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0 P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1 P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2 Figure 4 SAA-XC866 Pin Configuration, PG-TSSOP-38 Package (top view) Data Sheet MBC XTAL2 5 34 XTAL1 SSC DDC XC866 TMS DDP SSP 9 SAA-XC866 General Device Information RESET P3.5/COUT62_0 P3.4/CC62_0 P3 ...
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... COUT63_1 Output of Capture/Compare channel 3 Hi-Z MTSR_1 SSC Master Transmit Output/ Slave Receive Input CC62_1 Input/Output of Capture/Compare channel 2 Hi-Z MRST_1 SSC Master Receive Input/ Slave Transmit Output EXINT0_0 External Interrupt Input 0 COUT62_1 Output of Capture/Compare channel 2 10 SAA-XC866 General Device Information V1.5, 2010-09 ...
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... CCPOS1_1 CCU6 Hall Input 1 T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6 External Interrupt Input 6 PU CCPOS2_1 CCU6 Hall Input 2 T13HR_0 CCU6 Timer 13 Hardware Run Input P1.5 and P1.6 can be used as a software chip select output for the SSC. 11 SAA-XC866 General Device Information V1.5, 2010-09 ...
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... CCPOS2_0 CCU6 Hall Input 2 CTRAP_1 CCU6 Trap Input CC60_3 Input of Capture/Compare channel 0 AN2 Analog Input 2 Hi-Z AN3 Analog Input 3 Hi-Z AN4 Analog Input 4 Hi-Z AN5 Analog Input 5 Hi-Z AN6 Analog Input 6 Hi-Z AN7 Analog Input 7 12 SAA-XC866 General Device Information V1.5, 2010-09 ...
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... CCPOS2_2 CCU6 Hall Input 2 CC61_0 Input/Output of Capture/Compare channel 1 Hi-Z COUT61_0 Output of Capture/Compare channel 1 Hi-Z CC62_0 Input/Output of Capture/Compare channel 2 Hi-Z COUT62_0 Output of Capture/Compare channel 2 PD CTRAP_0 CCU6 Trap Input Hi-Z EXINT4 External Interrupt Input 4 COUT63_0 Output of Capture/Compare channel 3 13 SAA-XC866 General Device Information V1.5, 2010-09 ...
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... Core Supply Ground – ADC Reference Voltage – ADC Reference Ground Hi-Z External Oscillator Input (NC if not needed) Hi-Z External Oscillator Output (NC if not needed) PD Test Mode Select PU Reset Input PU Monitor & BootStrap Loader Control 14 SAA-XC866 General Device Information V1.5, 2010-09 ...
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... The SAA-XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the SAA-XC866 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. ...
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... Memory Organization The SAA-XC866 CPU operates in the following five address spaces: • 8 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 512 bytes of XRAM memory • a 128-byte Special Function Register area • 4/8/16 Kbytes of Flash program memory (Flash devices); or ...
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... Kbytes 0000 H Program Space 1) For SAA -XC866-1FR device, physically one 4KByte D-Flash bank is mapped to both address range 0000H - 0FFFH and A000H - AFFFH, and the shaded banks are not available. 2) For SAA -XC866-2FR device, the shaded banks are not available. Figure 6 Memory Map of SAA-XC866 Flash Devices ...
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... KBytes 2000 H User ROM 8 KBytes 0000 H Code Space 1) For SAA - XC866-2RR device, the shaded area is not available and Flash is 4 Kbytes. 2) For SAA - XC866-4RR device: ROM = (12+X) KBytes, Flash = (4-X) Kbytes. Figure 7 Memory Map of SAA-XC866 ROM Devices Data Sheet FFFF H F200 ...
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... Memory Protection Strategy The SAA-XC866 memory protection strategy includes: • Read-out protection: The Flash Memory can be enabled for read-out protection and ROM memory is always protected. • Program and erase protection: The Flash memory in all devices can be enabled for program and erase protection. ...
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... Erase B 01001XXX Erase B 01010XXX Erase B Others Erase Although no protection scheme can be considered infallible, the SAA-XC866 memory protection strategy provides a very high level of protection for a general purpose microcontroller. Data Sheet Functional Description Flash Banks to Erase when Unprotected All Banks P-Flash Bank Table 5 ...
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... The access to the standard SFR area is enabled. 1 The access to the mapped SFR area is enabled. rw Reserved Returns the last value if read; should be written with 1. r Reserved Returns 0 if read; should be written with 0. 21 SAA-XC866 Functional Description bringing the number H H Figure 8. Reset Value ...
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... SFR Data (to/from CPU) Figure 8 Address Extension by Mapping Data Sheet Standard Area (RMAP = 0) Module 1 SFRs SYSCON0.RMAP Module 2 SFRs rw Module n SFRs Mapped Area (RMAP = 1) Module (n+1) SFRs Module (n+2) SFRs Module m SFRs 22 SAA-XC866 Functional Description Direct Internal Data Memory Address V1.5, 2010-09 ...
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... Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the SAA-XC866 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs ...
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... The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The SAA-XC866 supports local address extension for: • Parallel Ports • Analog-to-Digital Converter (ADC) • ...
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... PAGE are saved in STx before being overwritten with the new value the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected. 25 SAA-XC866 Functional Description Reset Value PAGE rw V1.5, 2010-09 H ...
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... STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. r Reserved Returns 0 if read; should be written with 0. 26 SAA-XC866 Functional Description V1.5, 2010-09 ...
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... Password bits The Bit Protection Scheme only recognizes three patterns. 11000 Enables writing of the bit field MODE. B 10011 Opens access to writing of all protected bits. B 10101 Closes access to writing of all protected bits SAA-XC866 Functional Description , writing 10011 the bit B Reset Value PROTECT MODE _S ...
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... SAA-XC866 Register Overview The SFRs of the SAA-XC866 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in addresses of the bitaddressable SFRs appearing in bold typeface. The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = ...
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... VDDP Type r rwh rwh Bit Field BGSEL 0 H Type rw r Bit Field H Type Bit Field BGS SYNEN ERRSY H N Type rw rw rwh Bit Field H Type Bit Field H Type 29 SAA-XC866 Functional Description PCCIP PXM PX2 PSSC PADC PCCIP PXMH PX2H PSSCH PADC ...
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... H Type Bit Field H Type Bit Bit Field 0 WINB H EN Type r rw Bit Field H Type Bit Field H Type Bit Field H Type Bit Field H Type 30 SAA-XC866 Functional Description VERID SEL rw rw rwh rw T2_DIS CCU SSC _DIS _DIS OSC XPD OSC ORD PD SS RES ...
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... Type Bit Field Type Bit Field Type r rw Bit Field Type r rw Bit Field Type Bit Field Type Bit Field Type SAA-XC866 Functional Description STNR 0 PAGE w r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh ...
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... LCC H Type r rw Bit Field 0 LCC H Type r rw Bit Field 0 LCC H Type r rw Bit Field 0 LCC H Type r rw Bit Field 0 LCC H Type r rw Bit Field 0 LCC H Type r rw Bit Field 0 LCC H Type SAA-XC866 Functional Description STNR 0 PAGE w r rwh CTC CHNR ...
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... VFCTR WFR 0 H Type Bit Field VFCTR WFR 0 H Type Bit Field VFCTR WFR 0 H Type Bit Field VFCTR WFR 0 H Type Bit Field 0 H Type r 33 SAA-XC866 Functional Description DRC CHNR RESULT[9: DRC CHNR RESULT[9: DRC CHNR RESULT[9: DRC CHNR ...
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... ENSI RF H Type Bit Field EXTR ENSI RF H Type Bit Field EXTR ENSI RF H Type Bit Bit Field TF2 EXF2 H Type rwh rwh 34 SAA-XC866 Functional Description CHINF CHINF CHINF CHINF CHINF CHINC CHINC CHINC CHINC CHINC CHINS CHINS CHINS CHINS CHINS ...
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... Bit Field RSTR RIDLE RWHE RCHE H Type Bit Field 0 MCC63 H S Type r w Bit Field 0 MCC63 H R Type r w Bit Field H Type 35 SAA-XC866 Functional Description PREN T2PRE rw rw RC2[7:0] rwh RC2[15:8] rwh THL2[7:0] rwh THL2[15:8] rwh STNR 0 PAGE w r rwh CC63SL rw CC63SH ...
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... Bit Field CTM CDIR STE12 T12R H Type Bit Field 0 STE13 T13R H Type r rh Bit Field H Type Bit Field H Type Bit Field H Type 36 SAA-XC866 Functional Description CC60SH rwh CC61SL rwh CC61SH rwh CC62SL rwh CC62SH rwh CC63VL rh CC63VH rh T12PVL rwh T12PVH rwh ...
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... T13TED H Type r rw Bit Field 0 H Type r Bit Field MEN Type rw r Bit Field ECT13 Type rw r Bit Field 0 H Type r 37 SAA-XC866 Functional Description CC61VH rh CC62VL rh CC62VH rh MSEL60 rw MSEL62 rw ENCC ENCC ENCC ENCC ENCC 62R 61F 61R 60F ENT13 ENT13 ...
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... T13IM COUT COUT H 63PS 62PS Type rwh rwh rwh Bit Bit Field 0 H Type r Bit Field Type Bit Field 0 Type r 38 SAA-XC866 Functional Description TRPEN rw MCMP rh CURH EXPH rh rh ICC61F ICC61 ICC60F ICC60 CHE TRPS TRPF T13PM T13CM ISCC61 ISCC60 rw rw ...
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... SWBC HWB3C H Type rw rw Bit Field DVECT DRETR H Type rwh rwh Bit Field H Type Bit Field Type Bit Field 0 H Type r Bit Field H Type 39 SAA-XC866 Functional Description AREN BEN PEN REN TEN BSY rwh rwh rwh rwh TB_VALUE rw RB_VALUE rh BR_VALUE[7:0] rw BR_VALUE[15:8] ...
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... Data Sheet 1) of 32-byte for D-Flash and 32-byte for P-Flash 112.5 ns CCLK 2.6 ms SYS 102 ms SYS = 26.7 MHz ± 7 the maximum frequency range for Flash read access. 40 SAA-XC866 Functional Description f is used for sysmin V1.5, 2010-09 ...
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... Data Sheet 1) Size 125 ° Kbytes Kbytes Kbytes 3) 4 Kbytes 3) 1 Kbyte 3) 512 bytes 3) 128 bytes 41 SAA-XC866 Functional Description Remarks T = 125 to A 140 °C for 16-Kbyte Variant for 8-Kbyte Variant for 4-Kbyte Variant 1 Kbytes 256 bytes 128 bytes 32 bytes V1.5, 2010-09 ...
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... Flash Bank Sectorization The SAA-XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of embedded Flash memory. These Flash memory sizes are made up of two or four 4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash (P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization ...
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... Data Sheet 16 bytes 0000 ….. 0000 Program 1 H 1111 ….. 0000 Program 2 H Note: A Flash memory cell can be programmed H 32-byte write buffers 43 SAA-XC866 Functional Description Figure 12). 16 bytes 1111 ….. 1111 H H 0000 ….. 0000 H H from but not from V1.5, 2010-09 ...
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... Flash ECC Error Figure 13 Non-Maskable Interrupt Request Sources Data Sheet FNMIWDT NMIISR.0 NMIWDT NMICON.0 FNMIPLL NMIISR.1 NMIPLL NMICON.1 FNMIFLASH NMIISR.2 NMIFLASH >=1 FNMIVDD NMIISR.4 NMIVDD NMICON.4 FNMIVDDP NMIISR.5 NMIVDDP NMICON.5 FNMIECC NMIISR.6 NMIECC NMICON.6 44 SAA-XC866 Functional Description Non 0073 Maskable H Interrupt V1.5, 2010-09 ...
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... IEN0.1 TF1 TCON.7 001B ET1 IEN0.3 RI SCON.0 >=1 0023 TI ES IEN0.4 SCON.1 IE0 TCON.1 0003 EX0 IT0 IEN0.0 TCON.0 IE1 TCON.3 0013 EX1 IT1 IEN0.2 TCON.2 EA IEN0.7 45 SAA-XC866 Functional Description Highest Lowest Priority Level H IP.1/ IPH IP.3/ l IPH IP.4/ IPH IP.0/ IPH ...
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... FDCON.6 SYNEN FDCON.6 EXINT2 IRCON0.2 EX2 IEN1.2 EXINT2 EXINT3 IRCON0.3 EXINT4 IRCON0.4 EXM IEN1.3 >=1 EXINT5 IRCON0.5 EXINT6 IRCON0.6 46 SAA-XC866 Functional Description Highest Priority Level 002B H IP.5/ IPH.5 0043 H IP1.2/ IPH1.2 004B H IP1.3/ IPH1.3 EA IEN0.7 Bit-addressable Request flag is cleared by hardware V1.5, 2010-09 ...
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... ESSC IRCON1.1 IEN1.1 RIR IRCON1.2 CCU6SR0 IRCON3.0 ECCIP0 IEN1.4 CCU6SR1 IRCON3.4 ECCIP1 IEN1.5 CCU6SR2 IRCON4.0 ECCIP2 IEN1.6 CCU6SR3 IRCON4.4 ECCIP3 IEN1.7 47 SAA-XC866 Functional Description Highest Priority Level 0033 H IP1.0/ IPH1.0 003B H IP1.1/ IPH1.1 0053 H IP1.4/ IPH1.4 005B H IP1.5/ IPH1.5 0063 H IP1.6/ IPH1 ...
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... Interrupt Request Sources (Part 4) Data Sheet >=1 INPL.1 INPL.0 >=1 INPL.3 INPL.2 >=1 INPL.5 INPL.4 >=1 INPH.3 INPH.2 >=1 INPH.5 INPH.4 >=1 INPH.1 INPH.0 >=1 INPL.7 INPL.6 48 SAA-XC866 Functional Description CCU6 Interrupt node 0 CCU6 Interrupt node 1 CCU6 Interrupt node 2 CCU6 Interrupt node 3 V1.5, 2010-09 ...
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... Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the SAA-XC866 interrupt sources to the interrupt vector addresses and the corresponding interrupt source enable bits are summarized in Table 16 ...
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... H XINTR12 0063 H XINTR13 006B H Data Sheet ADC SSC External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 CCU6 INP0 CCU6 INP1 CCU6 INP2 CCU6 INP3 50 SAA-XC866 Functional Description EADC IEN1 ESSC EX2 EXM ECCIP0 ECCIP1 ECCIP2 ECCIP3 V1.5, 2010-09 ...
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... UART Interrupt Timer 2,Fractional Divider, LIN Interrupts 6 ADC Interrupt SSC Interrupt External Interrupt 2 External Interrupt [6:3] CCU6 Interrupt Node Pointer 0 CCU6 Interrupt Node Pointer 1 CCU6 Interrupt Node Pointer 2 CCU6 Interrupt Node Pointer 3 Data Sheet Functional Description Table 17. Level (highest SAA-XC866 V1.5, 2010-09 ...
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... Parallel Ports The SAA-XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general purpose input/output (GPIO perform alternate input/output functions for the on-chip peripherals ...
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... Alternate Select Register 1 AltDataOut 3 AltDataOut 2 AltDataOut1 Px_Data Data Register AltDataIn Figure 18 General Structure of Bidirectional Port Data Sheet enable enable Out In Schmitt Trigger 53 SAA-XC866 Functional Description VDDP Pull enable Up Device Output Driver Input Driver Pull enable Down Device Pad V1.5, 2010-09 Pin ...
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... Figure 19 General Structure of Input Port Data Sheet Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register enable In Driver Px_DATA Data Register Schmitt Trigger 54 SAA-XC866 Functional Description VDDP Pull enable Up Device Input Pull enable Down Device Pad V1.5, 2010-09 Pin ...
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... V for the core, memory, on-chip oscillator, and peripherals Figure 20 shows the SAA-XC866 power supply system. A power supply of 3 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design ...
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... Reset Control The SAA-XC866 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the SAA-XC866 is first powered up, the status of certain pins (see be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset ...
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... V DDP, DDC The second type of reset in SAA-XC866 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. To ensure the recognition of the hardware reset, pin RESET must be held low for at least 100 ns. ...
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... Disabled 3.7.2 Booting Scheme When the SAA-XC866 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0 ...
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... PLL Mode • Power-down mode support The CGU consists of an oscillator circuit and a PLL.In the SAA-XC866, the oscillator can be from either of these two sources: the on-chip oscillator (10 MHz) or the external oscillator (4 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated ...
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... Note: When oscillator clock is disconnected from PLL, the clock mode is PLL Base mode regardless of the setting of VCOBYP bit. System Frequency Selection For the SAA-XC866, the values of P and K are fixed to “1” and “2”, respectively. In order to obtain the required system frequency, f for different oscillator inputs. ...
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... Table 21 System frequency (f Oscillator f osc On-chip 10 MHz External 10 MHz 8 MHz 5 MHz Table 22 shows the VCO range for the SAA-XC866. Table 22 VCO Range f f VCOmin VCOmax 150 200 100 150 3.8.1 Recommended External Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source ...
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... Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. Data Sheet f Ex ternal Cloc Signal SAA-XC866 Functional Description XTAL1 XC866 Oscillator XTAL2 V SS Clock_EXOSC V1.5, 2010-09 ...
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... Flash Interface clock: CCLK3 = 80 MHz and CCLK = 26.7 MHz In addition, different clock frequency can output to pin CLKOUT(P0.0). The clock output frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the resulting output frequency has 50% duty cycle. the SAA-XC866. fosc PLL OSC ...
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... Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the peripherals, including CCU6, are divided by a common programmable factor defined by bit field CMCON.CLKREL. Power-down Oscillator and PLL are switched off. Data Sheet = 80 MHz) sys 64 SAA-XC866 Functional Description V1.5, 2010-09 ...
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... Power Saving Modes The power saving modes of the SAA-XC866 provide flexible power consumption through a combination of techniques, including: • Stopping the CPU clock • Stopping the clocks of individual system components • Reducing clock speed of some peripheral components • Power-down of the entire system with fast restart capability ...
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... WDT from causing an SAA-XC866 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the SAA-XC866 will be aborted in a user-specified time period. In debug mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging ...
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... WDT Timing Diagram Data Sheet count, after which the system is reset H ( × ) × WDTIN – = ----------------------------------------------------------------------------------------------------- - f PCLK 28. This period can be calculated using the same formula by No refresh Refresh allowed allowed 67 SAA-XC866 Functional Description / PCLK PCLK × WDTREL 2 time V1.5, 2010- /128 WDT ...
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... Some numbers are rounded to 3 significant digits. Table 24 Watchdog Time Ranges Reload value Prescaler for f in WDTREL 2 (WDTIN = 0) 26.7 MHz 19.2 μ 2. 4. Data Sheet PCLK 128 (WDTIN = 1) 26.7 MHz 1.23 ms 159 ms 315 ms 68 SAA-XC866 Functional Description V1.5, 2010-09 ...
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... Timer 1. Data Sheet Baud Rate f /2 PCLK Variable f / PCLK PCLK Variable / /64. The variable baud rate is set by PCLK PCLK 69 SAA-XC866 Functional Description Table 25. Data is /64 V1.5, 2010-09 ...
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... Fractional Divider FDSTEP 1 FDEN&FDM 1 0 Adder f 00 DIV FDRES (overflow) MOD ‘0’ the fractional divider is disabled (FDEN = 0). For baud rate ) defined by bit field BRPRE in register BCON 70 SAA-XC866 Functional Description 8-Bit Reload Value 8-Bit Baud Rate Timer R NDOV Section 3.12. V1.5, 2010-09 ...
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... Data Sheet f PCLK × BR_VALUE + 1 f PCLK ---------------------------------------------------------------------------------- - = BRPRE × × BR_VALUE Reload Value BRPRE ) (BR_VALUE + ( 174 ( 174 ( 174 ( SAA-XC866 Functional Description BRPRE × ( BR_VALUE + STEP × -------------- - 256 ) + 1 /32. Hence, for a module f PCLK Deviation Error ) -0. -0. -0. -0. V1.5, 2010- > 1 ...
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... Table 27 Deviation Error for UART with Fractional Divider enabled f Prescaling Factor PCLK BRPRE (2 ) 26.67 MHz 1 13.33 MHz 1 6.67 MHz 1 Data Sheet Reload Value STEP (BR_VALUE + 177 ( 248 ( 212 ( SAA-XC866 Functional Description Deviation Error ) +0. +0. -0. V1.5, 2010-09 ...
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... MOD The output frequency in normal divider mode is derived as follows: Data Sheet SMOD × ---------------------------------------------------- - × × 256 TH1 f , where n is defined by 256 - STEP. DIV 1 × ----------------------------- - MOD DIV 256 STEP – 73 SAA-XC866 Functional Description f PCLK ) – Figure 29). Once the V1.5, 2010-09 [3.1] [3.2] ...
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... UART data. Data Sheet Figure 30. The frame consists of the: Frame slot Frame Response space Response Data 2 Data 1 identifier 74 SAA-XC866 Functional Description ), and ID field H Inter- frame space Checksum Data N V1.5, 2010-09 ...
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... STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame. Data Sheet Functional Description 75 SAA-XC866 V1.5, 2010-09 ...
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... Programmable clock/data phase: data shift with leading or trailing edge of the shift clock • Variable baud rate • Compatible with Serial Peripheral Interface (SPI) • Interrupt generation – transmitter empty condition – receiver full condition – error condition (receive, phase, baud rate, transmit error) Data Sheet Functional Description 76 SAA-XC866 V1.5, 2010-09 ...
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... Clock RIR TIR SSC Control Block Register CON EIR Status Control Pin 16-Bit Shift Control Register Receive Buffer Register RB Internal Bus 77 SAA-XC866 Functional Description SS_CLK MS_CLK Receive Int. Request Transmit Int. Request Error Int. Request TXD(Master) RXD(Slave) TXD(Slave) RXD(Master) V1.5, 2010-09 ...
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... The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow. 3 Timer 0 operates as two 8-bit timers The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled. Data Sheet Functional Description 78 SAA-XC866 V1.5, 2010-09 ...
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... Reload value fixed at 0000 • Capture event triggered by falling/rising edge at pin T2EX • Captured timer value stored in register RC2 • Interrupt is generated with reload or capture event Data Sheet Functional Description , underflow at value defined in register overflow at FFFF SAA-XC866 H H V1.5, 2010-09 ...
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... Automatic rotational speed measurement for block commutation • Integrated error handling • Fast emergency stop without CPU load via external signal (CTRAP) • Control modes for multi-channel AC-drives • Output levels can be selected and adapted to the power stage Data Sheet Functional Description 80 SAA-XC866 V1.5, 2010-09 ...
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... T13 interrupt control Figure 32 CCU6 Block Diagram Data Sheet Figure module kernel compare channel 0 1 dead- channel 1 time 1 control channel 2 1 channel 3 compare input / output control port control 81 SAA-XC866 Functional Description 32. multi- trap channel control control CCU6_block_diagram V1.5, 2010-09 1 ...
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... Analog-to-Digital Converter The SAA-XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2. ...
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... ADC is limited to a maximum frequency of 10 MHz. ADCI f ADCD CTC ÷ 32 ÷ ADCI MUX ÷ 3 ÷ 2 clock prescaler ≤ Condition MHz, where t ADCI 83 SAA-XC866 Functional Description arbiter registers interrupts digital part analog components analog part 1 ADCI = f ADCI V1.5, 2010-09 ADCI ...
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... B becomes too low during slow-down mode. ADC ) SYN ) Conversion Phase CONV 84 SAA-XC866 Functional Description frequency can be selected as ADCI Analog Clock f 13.3 MHz (N.A) 8.9 MHz 6.7 MHz 833.3 kHz when f B does not exceed ADCI ...
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... The dedicated MBC pin is used for external configuration and debugging control. Note: All the debug functionality described here can normally be used only after SAA- XC866 has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary) ...
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... This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04 also true immediately after reset. The JTAG ID register contents for the SAA-XC866 devices are given in Table 31 JTAG ID Summary Device Type ...
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... Table 31 JTAG ID Summary ROM SAA-XC866L-4RRA SAA-XC866-4RRA SAA-XC866L-2RRA SAA-XC866-2RRA 3.20 Identification Register The SAA-XC866 identity register is located at Page 1 of address B3 ID Identity Register 7 6 PRODID Field Bits VERID [2:0] PRODID [7:3] Data Sheet 1013 9083 1013 9083 1013 9083 1013 9083 Type Description ...
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... Section 4.2 4.1.1 Parameter Interpretation The parameters listed in this section represent partly the characteristics of the SAA- XC866 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column: • ...
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... Absolute Maximum Rating Maximum ratings are the extreme limits to which the SAA-XC866 can be subjected to without permanent damage. Table 32 Absolute Maximum Rating Parameters Parameter Ambient temperature Storage temperature Junction temperature Voltage on power supply pin with respect Voltage on core supply pin with ...
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... Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the SAA-XC866. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 33 Operating Condition Parameters Parameter Digital power supply voltage Digital power supply voltage ...
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... IHP0 DDP V DDP 0.7 × – IHR V DDP 0.75 × – IHT V DDP 0.08 × HYS CC – V DDP 0.07 × HYSX CC – V DDC 91 SAA-XC866 Electrical Parameters Unit Test Conditions - CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode ...
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... OZ1 I CC -10 10 ILX Σ – – 0 – Σ – – 80 MVDDP SR I – 80 MVSS SR 92 SAA-XC866 Electrical Parameters Unit Test Conditions V V µA V IH,min V µA IL,max V µA IL,max V µA IH,min V V µA 0 < < DDP ≤ 140° µ V1.5, 2010-09 ...
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... HYS CC – V DDP 0.07 × HYSX CC – V DDC 0.3 × ILX SS V 0.5 DDC 0.7 × IHX DDC V + 0.5 DDC 93 SAA-XC866 Electrical Parameters Unit Test Conditions 2 -2 CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode V ...
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... SR – Σ – – 80 MVDDP SR I – 80 MVSS SR ) will flow if an overload current flows through an adjacent pin. TMS pin and INJ 94 SAA-XC866 Electrical Parameters Unit Test Conditions V µA IH,min V µA IL,max V µA IL,max V µA IH,min V V µA 0 < < DDP ≤ 140°C ...
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... The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage. Data Sheet Symbol 2.2 DDCPW V CC 2.0 DDCBO V CC 0.9 DDCRDR V CC 1.3 DDCBOPD 3.3 DDPPW V CC 1.3 DDCPOR 95 SAA-XC866 Electrical Parameters V DDPPW V DDCPW V DDCBO V DDCRDR V DDCBOPD Limit Values min. typ. max. 2.3 2.4 2.1 2.2 1.0 1.1 1.5 1.7 4 ...
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... CC | – 1 – – 1 – – 1 – – – 1 – – 1 SAA-XC866 Electrical Parameters ) must Range) DDP Unit Test Conditions/ Remarks MHz module clock MHz internal analog 1) clock See Figure 33 1) µs 1) µs 2) LSB 8-bit conversion. LSB 10-bit conversion. ...
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... CC – – – 5.0 V. AGND DDP I ). The amount of error current depends on the OZ ). The additional error current may distort the input voltage on analog inputs. 97 SAA-XC866 Electrical Parameters Range) DDP Unit Test Conditions/ Remarks 1)3) I – > 1)3) – I < 1)4) pF 1)5) ...
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... CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC (for 8-bit and 10-bit conversion respectively ADC ADC Data Sheet ANx V AGNDx Reference Voltage Input Circuitry R V AREFx V AGNDx × × STC where , SAA-XC866 Electrical Parameters Analog Input Circuitry R AIN AINSW AREF AREFSW V1.5, 2010-09 ...
Page 102
... Data Sheet Symbol Limit Values 1) typ. max. I 22.6 24.5 DDP I 17.2 19.7 DDP I 7.2 8.2 DDP I 7.1 8 DDP = + 25 °C and RESET = DDP , RESET = SAA-XC866 Electrical Parameters Unit Test Condition 5.0 V. DDP = + 140 °C and V = 5.5 V). A DDP V . DDP . DDP V1.5, 2010- ...
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... Not subject to production test, verified by design/characterization. Data Sheet Symbol Limit Values 1) typ. max PDP - 5.0 V. DDP V = 5.5 V. DDP = + 140 ° DDP AGND SS 100 SAA-XC866 Electrical Parameters Unit Test Condition °C. 4) µ °C. 4)5) µ RXD/INT0 = ; rest of the ports DDP V1.5, 2010-09 ...
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... DDP 90% 10 Figure 38 Rise/Fall Time Parameters V DDP V DDE V SS Figure 39 Testing Waveform, Output Delay + 0 Load V - 0.1 V Load Figure 40 Testing Waveform, Output High Impedance Data Sheet and Figure 40 Test Points Timing Reference Points 101 SAA-XC866 Electrical Parameters 90% 10 DDE - 0 0 V1.5, 2010-09 ...
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... Additional rise/fall time valid for C 4) Additional rise/fall time valid for C V DDP 10 Figure 41 Rise/Fall Times Parameters Data Sheet Symbol Limit Values min. max – – 20pF - 100pF @ 0.125 ns/pF 20pF - 100pF @ 0.225 ns/pF 102 SAA-XC866 Electrical Parameters Unit Test Conditions pF pF. 90% 10 V1.5, 2010-09 ...
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... DDC PLL unlock t LOCK Reset Initialization t FINIT 3) 2)ENPS control 3)As Programmed III) until Flash go II)until PLL is locked to Ready-to-Read 103 SAA-XC866 Electrical Parameters Unit Test Conditions µs V µs rise time DDP (10% – 90%) ≤ 1)2) 500µ ...
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... CC -1.0 – 1 25°C. A 104 SAA-XC866 Electrical Parameters 1) conditions with respect over NOM lifetime and temperature (125°C to 140°C), for one device after trimming with respect over NOM lifetime and temperature (−10°C to 125°C), for one ...
Page 108
... TCK clock fall time 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 0.5 V DDP TCK Figure 43 TCK Clock Timing Data Sheet Symbol t TCK TCK 105 SAA-XC866 Electrical Parameters = 50 pF) L Limits min max − − − − − 0 ...
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... TDO valid output to high impedance from TCK 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. TCK TMS TDI TDO Figure 44 JTAG Timing Data Sheet 106 SAA-XC866 Electrical Parameters = 50 pF) L Symbol Limits min max − 8.0 1 − 5.0 2 − 11.0 1 − 6 − ...
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... This timing is based on the following setup: CON.PH = CON. Figure 45 SSC Master Mode Timing Data Sheet Symbol 26.7MHz 74.9ns. T CPU Data valid t 1 107 SAA-XC866 Electrical Parameters L Limit Values min. max. 2) – SSC 8 – – is the CPU clock period. CPU t 1 SSC_Tmg1 V1.5, 2010- pF) Unit ...
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... R CC – 15.7 TJC R CC – 39.2 TJL ), the lead and the ambient (R TCA 108 SAA-XC866 Package and Reliability Unit Notes K/W – K/W – ) are to be TLA ), the junction and the lead TJC ), the lead and the ambient (R TCA × ...
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... Package Outline Figure 46 PG-TSSOP-38-4 Package Outline Data Sheet Package and Reliability 109 SAA-XC866 V1.5, 2010-09 ...
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... Quality Declaration Table 46 shows the characteristics of the quality parameters in the SAA-XC866. Table 46 Quality Parameters Parameter Operation Lifetime when the device is used at the 1)2) four stated T A Operation Lifetime when the device is used at the 1)2) two stated T A Weighted Average 2)3) ...
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... Published by Infineon Technologies AG ...