SAA-XC866-2FRA 5V BE Infineon Technologies, SAA-XC866-2FRA 5V BE Datasheet - Page 62

• Manufacturer Part Number: SAA-XC866-2FRA 5V BE
• Description: IC MCU 8BIT FLASH PG-TSSOP-38
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAA-XC866-2FRA 5V BE

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 38-TFSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: MCBXC866 - BOARD EVAL FOR INFINEON XC86X
• Other names: AX8662FRABEXT; SAA-XC866-2FRA BE; SAA-XC866-2FRA5VBEINTR; SAA-XC866-2FRABEINTR; SAA-XC866-2FRABEINTR; SP000281789

3.8
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
SAA-XC866. The power consumption is indirectly proportional to the frequency,
whereas the performance of the microcontroller is directly proportional to the frequency.
During user program execution, the frequency can be programmed for an optimal ratio
between performance and power consumption. Therefore the power consumption can
be adapted to the actual application state.
Features:
• Phase-Locked Loop (PLL) for multiplying clock source by different factors
• PLL Base Mode
• Prescaler Mode
• PLL Mode
• Power-down mode support
The CGU consists of an oscillator circuit and a PLL.In the SAA-XC866, the oscillator can
be from either of these two sources: the on-chip oscillator (10 MHz) or the external
oscillator (4 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip
oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip
oscillator will be used by default.The external oscillator can be selected via software. In
addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock
detection. This allows emergency routines to be executed for system recovery or to
perform system shut down.
Figure 23
Data Sheet
OSC
Clock Generation Unit
fosc
CGU Block Diagram
P:1
OSCDISC
fp
fn
osc fail
detect
detect
core
lock
PLL
NDIV
N:1
59
fvco
VCOBYP
1
0
K:1
Functional Description
fsys
SAA-XC866
V1.5, 2010-09
OSCR
LOCK