SAA-XC866-2FRA 5V BE Infineon Technologies, SAA-XC866-2FRA 5V BE Datasheet - Page 106

• Manufacturer Part Number: SAA-XC866-2FRA 5V BE
• Description: IC MCU 8BIT FLASH PG-TSSOP-38
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAA-XC866-2FRA 5V BE

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 38-TFSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: MCBXC866 - BOARD EVAL FOR INFINEON XC86X
• Other names: AX8662FRABEXT; SAA-XC866-2FRA BE; SAA-XC866-2FRA5VBEINTR; SAA-XC866-2FRABEINTR; SAA-XC866-2FRABEINTR; SP000281789

4.3.3
Table 40
Parameter
Pad operating voltage
On-Chip Oscillator
start-up time
Flash initialization time
RESET hold time
PLL lock-in in time
PLL accumulated jitter D
1)
2)
3)
Figure 42
Data Sheet
Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
RESET signal has to be active (low) until
PLL lock at 80 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 40 and P = 1.
Flash State
RESET
VDDC
VDDP
OSC
PLL
Pads
t
RST
Power-on Reset and PLL Timing
1)
Power-on Reset Timing
I)until EVR is stable
2)
Power-On Reset and PLL Timing (Operating Conditions apply)
V
PAD
1)Pad state undefined
t
Symbol
V
t
t
t
t
OSCST
OSCST
FINIT
RST
LOCK
PAD
P
Reset
II)until PLL is locked
CC
CC –
SR
CC –
CC 2.3
PLL unlock
V
DDC
min. typ.
–
–
–
t
LOCK
2)ENPS control 3)As Programmed
Limit Values
has reached 90% of its maximum value (typ. 2.5V).
103
–
–
160
500
–
–
3)
to Ready-to-Read
III) until Flash go
Initialization
max.
–
500
–
–
200
0.7
t
FINIT
Unit Test Conditions
V
ns
µs
µs
µs
ns
IV) CPU reset is released; Boot
ROM software begin execution
PLL lock
1)
1)
1)
V
(10% – 90%) ≤
500µs
1)
1)3)
Ready to Read
Electrical Parameters
DDP
rise time
1)2)
SAA-XC866
V1.5, 2010-09