SAA-XC866-2FRA 5V BE Infineon Technologies, SAA-XC866-2FRA 5V BE Datasheet - Page 88

• Manufacturer Part Number: SAA-XC866-2FRA 5V BE
• Description: IC MCU 8BIT FLASH PG-TSSOP-38
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAA-XC866-2FRA 5V BE

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 38-TFSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: MCBXC866 - BOARD EVAL FOR INFINEON XC86X
• Other names: AX8662FRABEXT; SAA-XC866-2FRA BE; SAA-XC866-2FRA5VBEINTR; SAA-XC866-2FRABEINTR; SAA-XC866-2FRABEINTR; SP000281789

3.19
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
• use the built-in debug functionality of the XC800 Core
• add a minimum of hardware overhead
• provide support for most of the operations by a Monitor Program
• use standard interfaces to communicate with the Host (a Debugger)
Features:
• Set breakpoints on instruction address and within a specified address range
• Set breakpoints on internal RAM address
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks
• Step through the program code
The OCDS functional blocks are shown in
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals. After processing memory
address and control signals from the core, the MMC provides proper access to the
dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for
work-data and Monitor-stack). The OCDS system is accessed through the JTAG
which is an interface dedicated exclusively for testing and debugging activities and is not
normally used in an application. The dedicated MBC pin is used for external
configuration and debugging control.
Note: All the debug functionality described here can normally be used only after SAA-
1)
Data Sheet
The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
XC866 has been started in OCDS mode.
On-Chip Debug Support
Figure
85
35. The Monitor Mode Control (MMC)
Functional Description
SAA-XC866
V1.5, 2010-09
1)
,