AD9891KBC Analog Devices Inc, AD9891KBC Datasheet
AD9891KBC
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AD9891KBC Summary of contents
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FEATURES AD9891: 10-Bit 20 MHz Version AD9895: 12-Bit 30 MHz Version Correlated Double Sampler (CDS Pixel Gain Amplifier ( PxGA 10-Bit Variable Gain Amplifier (VGA) 10-Bit 20 MHz A/D Converter (AD9891) ...
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AD9891/AD9895 TABLE OF CONTENTS SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 DIGITAL SPECIFICATIONS . ...
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AD9891/AD9895–SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD1, AVDD2 (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (H1–H4 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) POWER DISSIPATION–AD9891 (See TPC 1 for Power Curves) 20 ...
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AD9891/AD9895 AD9891–ANALOG SPECIFICATIONS Parameter CDS Gain Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (PxGA ...
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AD9895–ANALOG SPECIFICATIONS Parameter CDS Gain Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (PxGA Code ...
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... CLIDLY SCLK PACKAGE THERMAL CHARACTERISTICS Thermal Resistance = 61°C 29.7°C/W JC Unit Model V V AD9891KBC –20°C to +85°C V AD9895KBC –20°C to +85° °C 150 °C 350 –6– MHz [AD9891 MHz [AD9895], unless CLI Min Typ Max 33 16.7 ...
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Pin Mnemonic Type Description Vertical Sync Pulse (Input for Slave Mode, Output for Master Mode Horizontal Sync Pulse (Input for Slave Mode, Output for Master Mode) C1 SYNC DI External System Sync Input ...
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AD9891/AD9895 2 Pin Mnemonic Type Description Vertical Sync Pulse (Input for Slave Mode, Output for Master Mode Horizontal Sync Pulse (Input for Slave Mode, Output for Master Mode) C1 SYNC DI External System Sync ...
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SPECIFICATION DEFINITIONS Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution ...
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AD9891/AD9895–Typical Performance Characteristics 440 RGVDD = HVDD = 5.0V 400 V = 3.3V DD 360 V = 3.0V DD 320 V = 2.7V DD 280 240 200 10 15 SAMPLE RATE – MHz TPC 1. AD9891 Power vs. Sample Rate ...
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SYSTEM OVERVIEW Figure 5 shows the typical system block diagram for the AD9891/ AD9895 used in Master Mode. The CCD output is processed by the AD9891/AD9895’s AFE circuitry, which consists of a CDS, PxGA, VGA, black level clamp, and an ...
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AD9891/AD9895 PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9891/AD9895 generates flexible, high speed timing signals using the Precision Timing core. This core is the founda- tion for generating the timing used for both the CCD and the AFE: the reset ...
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Figure 10 shows the range and default locations of the high speed clock signals. H-Driver and RG Outputs In addition to the programmable timing positions, the AD9891/ AD9895 features on-chip output drivers for the RG and ...
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AD9891/AD9895 P[0] POSITION PIXEL PERIOD RGr[0] RG Hr[0] H1/H3 CCD SIGNAL NOTES ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. Figure 10. High Speed Clock ...
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HORIZONTAL CLAMPING AND BLANKING The AD9891/AD9895’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal, which are then organized into multiple regions ...
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AD9891/AD9895 zontal sequences four SCPs are available to divide the readout into four separate regions, as shown in Figure 16. The SCP0 is always hard-coded to line 0, and SCP1–SCP3 are register programmable. During each region bound by ...
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VERTICAL TIMING GENERATION The AD9891/AD9895 provide a very flexible solution for gener- ating vertical CCD timing and can support multiple CCDs and different system architectures. The 4-phase vertical transfer clocks V1–V4 are used to shift each line of pixels into ...
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AD9891/AD9895 Individual Vertical Sequences To generate the individual vertical sequences or patterns shown in Figure 18, five registers are required for each sequence. Table VII summarizes these registers and their respective bit lengths. The start polarity (VTPPOL) determines the starting ...
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Individual Vertical Regions The AD9891/AD9895 arranges the individual sequences into re- gions through the use of Sequence Pointers (SPTR). Within each region, different sequences may be assigned to each V-clock output. Figure 21 shows the programmability of each region and ...
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AD9891/AD9895 Register Length Range HDLEN 12b 0–4095 Pixels VxSTART 12b 0–4095 Pixel Location VxSPTRFIRST 4b Sequence 0–11 VxINVFIRST 1b High/Low x is the V-output from 1–4. Complete Field: Combining the Regions The individual regions are combined into a complete field ...
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Vertical Sequence Alternation The AD9891/AD9895 also supports line-by-line alternation of vertical sequences within any region, as shown in Figure 23. Table X summarizes the additional registers used to support differ- ent alternation patterns. To create an alternating vertical pattern, REGION ...
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AD9891/AD9895 Second Vertical Sequence During VSG Lines Most CCDs require additional vertical timing during the sensor gate line. The AD9891/AD9895 supports the option to output a second set of sequences for V1–V4 during the line when the sen- sor gates ...
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HD VSG1– VSGX Figure 25. Example of Second Sequences During Sensor Gate Line VD HD LINE 0 LINE 1 V1–V4 REGION AREA 0 Figure 26. Example of Sweep Region for High Speed Vertical Shift REV. A ...
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AD9891/AD9895 Vertical Multiplier Mode To generate very wide vertical timing pulses, a vertical region may be configured into Multiplier Mode. This mode uses the vertical sequence registers in a slightly different manner. Multiplier Mode can be used to support unusual ...
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ACTIVE IMAGE AREA STORAGE AREA V7 V8 Figure 28. Example of Frame Transfer CCD Mode using V1–V8 The frame transfer CCD also requires additional timing control when decimating the image for Preview Mode. ...
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AD9891/AD9895 Table XIII contains the summary of the VSG Registers. The AD9891/AD9895 has eight SG outputs, VSG1–VSG8. Each of the outputs can be assigned to one of four programmed sequences by using the SGSEL1–SGSEL8 Registers. Each sequence is generated in ...
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SUBCK Suppression Normally, the SUBCKs will begin to pulse on the line following the sensor gate line (VSG). With some CCDs, the SUBCKs need to be suppressed for one or more lines following the VSG line. The SUBCKSUPPRESS Register allows ...
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AD9891/AD9895 VD VSG1– VSG8 SUBCK MSHUT 1 2 MSHUT PROGRAMMABLE SETTINGS: 1: ACTIVE POLARITY 2: ON-POSITION IS VD UPDATED AND MAY BE SWITCHED ON AT ANY TIME 3: OFF-POSITION CAN BE PROGRAMMED ANYWHERE FROM THE FIELD OF LAST SUBCK UNTIL ...
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SERIAL WRITES VD VSG SUBCK STROBE MSHUT MECHANICAL SHUTTER VSUB Figure 35. Exposure and Readout of Interlaced Frame Example of Exposure and Readout of Interlaced Frame Figure 35 shows the sequence of events for a typical exposure and readout operation ...
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AD9891/AD9895 ANALOG FRONT END DESCRIPTION AND OPERATION The AD9891/AD9895 AFE signal processing chain is shown in Figure 36. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. AFE Register de- tails are ...
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Mosaic Separate Steering Mode accommodates the popular “Bayer” arrangement of Red, Green, and Blue filters (see Figure 38a). The same Bayer pattern can also be interlaced, and the Mosaic Interlaced Mode should be used with this type of ...
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AD9891/AD9895 FLD VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN STEERING TO “0101” LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN STEERING BETWEEN “0101” AND ...
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FLD VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “01230123” LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “01230123” ...
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AD9891/AD9895 VDD (INPUT) CLI (INPUT) t PWR SERIAL WRITES SYNC (INPUT) VD (OUTPUT) HD (OUTPUT) H2/H4 DIGITAL OUTPUTS H1/H3, RG, DCLK Figure 42. Recommended Power-Up Sequence and Synchronization, Master Mode POWER-UP AND SYNCHRONIZATION Recommended Power-Up Sequence for Master Mode When ...
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SYNC VD HD H124, RG, V1–V4, VSG, SUBCK NOTES 1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR x025). 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD ...
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AD9891/AD9895 I/O Block OUT_CONT== LOW AFE ON Timing Core ON CLO Oscillator ON V1 LOW V2 LOW V3 HIGH V4 HIGH VSG1 HIGH VSG2 HIGH VSG3 HIGH VSG4 HIGH VSG5 HIGH VSG6 HIGH VSG7 HIGH VSG8 HIGH SUBCK HIGH VSUB ...
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HORIZONTAL TIMING SEQUENCE EXAMPLE Figure 45 shows an example CCD layout. The horizontal regis- ter contains 28 dummy pixels that will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines ...
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AD9891/AD9895 SEQUENCE 2: VERTICAL OPTICAL BLACK LINES VERTICAL SHIFT CCDIN OPTICAL BLACK SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 47. Horizontal Sequences During Vertical Optical Black Pixels SEQUENCE 3: EFFECTIVE PIXEL LINES OPTICAL BLACK VERTICAL SHIFT CCDIN SHP ...
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VERTICAL TIMING EXAMPLE Figure 49 shows an example CCD timing chart for an interlaced readout. Each field can be broken down into four separate region areas. The vertical region change positions (RCPs) will set the line boundaries for each region ...
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AD9891/AD9895 CIRCUIT LAYOUT INFORMATION The AD9891/AD9895 Typical Circuit Connection is shown in Figure 50. Note that Pins E1 and E2 will be No Connects when using the AD9891. The PCB layout is critical in achieving good image quality from the ...
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SERIAL INTERFACE TIMING All of the internal registers of the AD9891/AD9895 are accessed through a 3-wire serial interface. Each register consists of a 10-bit address and a 6-bit data-word. Both the 10-bit address and 6-bit data-word are written starting with ...
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AD9891/AD9895 NOTES ON REGISTER LISTING 1. Registers larger than six bits occupy two adjacent addresses. When writing to these registers, the lower address contain- ing the least significant data bits should be written to first. The data for both addresses ...
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Bit Address Content Width 00 [5: [1: [5: [3: [5: [1: [5: [5: [5: [5: [5:0] 6 Bit Address Content ...
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AD9891/AD9895 Bit Address Content Width 064 0 065 [5:0] 6 066 [5:0] 6 067 [5:0] 6 068 [5:0] 6 069 [5:0] 6 06A [5:0] 6 06B [5:0] 6 06C [5:0] 6 06D [5:0] 6 06E [5:0] 6 06F [5:0] 6 ...
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Bit Address Content Width 08D [0] 1 08E [5:0] 6 08F [5:0] 6 090 [5:0] 6 091 [5:0] 6 092 [0] 1 093 [5:0] 6 094 [5:0] 6 095 [5:0] 6 096 [5:0] 6 097 [0] 1 098 [5:0] 6 ...
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AD9891/AD9895 Bit Address Content Width 0BD [0] 1 0BE [5:0] 6 0BF [5:0] 6 0C0 [5:0] 6 0C1 [5:0] 6 0C2 [0] 1 0C3 [5:0] 6 0C4 [5:0] 6 0C5 [5:0] 6 0C6 [5:0] 6 0C7 [0] 1 0C8 [5:0] ...
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Bit Address Content Width 0EB [0] 1 0EC [0] 1 0ED [5:0] 6 0EE [5:0] 6 0EF [4:0] 6 0F0 [5:0] 6 0F1 [5:0] 6 0F2 [5:0] 6 0F3 [5:0] 6 Bit Address Content Width 0F4 [0] 1 0F5 [5:0] ...
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AD9891/AD9895 Bit Address Content Width 11C [5:0] 6 11D [3:0] 4 11E [5:0] 6 11F [11:6] 6 120 [0] 1 121 [5:0] 6 122 [5:0] 6 123 [5:0] 6 124 [5:0] 6 125 [5:0] 6 126 [5:0] 6 127 [5:0] ...
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Bit Address Content Width 154 [0] 1 155 [5:0] 6 156 [3:0] 4 157 [5:0] 6 158 [3:0] 4 159 [5:0] 6 15A [3:0] 4 15B [5:0] 6 15C [0] 1 15D [5:0] 6 15E [3:0] 4 15F [5:0] 6 ...
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AD9891/AD9895 Bit Address Content Width 189 [0] 1 18A [3:0] 4 18B [0] 1 18C [5:0] 6 18D [5:0] 6 18E [3:0] 4 18F [0] 1 190 [3:0] 4 191 [0] 1 192 [5:0] 6 193 [5:0] 6 194 [3:0] ...
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Bit Address Content Width 1BF [5:0] 6 1C0 [3:0] 4 1C1 [0] 1 1C2 [3:0] 4 1C3 [0] 1 1C4 [5:0] 6 1C5 [5:0] 6 1C6 [5:0] 6 1C7 [5:0] 6 1C8 [5:0] 6 1C9 [5:0] 6 1CA [5:0] 6 ...
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AD9891/AD9895 Bit Address Content Width 1F6 [5:0] 6 1F7 [5:0] 6 1F8 [1:0] 2 1F9 [0] 1 1FA [3:0] 4 1FB [0] 1 1FC [3:0] 4 1FD [0] 1 1FE [5:0] 6 1FF [5:0] 6 200 [3:0] 4 201 [0] ...
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Bit Address Content Width 22D [0] 1 22E [3:0] 4 22F [0] 1 230 [5:0] 6 231 [5:0] 6 232 [3:0] 4 233 [0] 1 234 [3:0] 4 235 [0] 1 236 [5:0] 6 237 [5:0] 6 238 [5:0] 6 ...
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AD9891/AD9895 Bit Address Content Width 251 [0] 1 252 [5:0] 6 253 [5:0] 6 254 [5:0] 6 255 [5:0] 6 256 [0] 1 257 [5:0] 6 258 [5:0] 6 259 [5:0] 6 25A [5:0] 6 25B [0] 1 25C [5:0] ...
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Table XXX. SUBCK, VSUB, MSHUT Register Map (continued) Bit Address Content Width 283 [0] 1 284 [0] 1 285 [5:0] 6 286 [5:0] 6 287 [0] 1 288 [0] 1 289 [5:0] 6 28A [5:0] 6 28B [5:0] 6 28C ...
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AD9891/AD9895 Bit Content Width OPRMODE [7:0] [1:0] 2’h0 2’h1 2’h2 2’h3 [2] [3] [4] [5] [6] [7] CTLMODE [5:0] [2:0] 3’h0 3’h1 3’h2 3’h3 3’h4 3’h5 3’h6 3’h7 [3] [4] 1’h0 1’h1 [5] 1’h0 1’h1 Table XXXI. AFE Register Breakdown ...
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MIN 1.70 MAX Revision History Location 8/02—Data Sheet changed from REV REV. A. Added AD9895 part . . . . . . . . . . . . . . . . . . . . . ...
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