AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 53

• Manufacturer Part Number: AD9891KBC
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9891KBC

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Address
22D
22E
22F
230
231
232
233
234
235
236
237
238
239
23A
23B
23C
23D
23E
23F
240
241
242
243
244
245
246
247
248
249
24A
24B
24C
24D
24E
24F
250
REV. A
Content
[0]
[3:0]
[0]
[5:0]
[5:0]
[3:0]
[0]
[3:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[3:0]
[0]
[5:0]
[5:0]
[3:0]
[0]
[5:0]
[5:0]
[3:0]
[0]
[5:0]
[5:0]
[3:0]
[0]
[5:0]
[5:0]
Bit
Width
1
4
1
6
6
4
1
4
1
6
6
6
6
6
6
6
6
6
6
1
4
1
6
6
4
1
6
6
4
1
6
6
4
1
6
6
Default
Value
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
02
00
10
10
03
00
2A
11
04
00
32
0F
05
00
2E
10
Table XXVIII. V1–V8 Register Map (continued)
V4INVFIRST4
V4SPTRSECOND4
V4INVSECOND4
V4_7START4[5:0]
V4_7START4[11:6]
V4SPTRFIRST4
V4INVFIRST4
V4SPTRSECOND4
V4_8START4[5:0]
V4_8START4[11:6]
V1_4FREEZE4[5:0]
V1_4FREEZE4[11:6]
V1_4RESUME4[5:0]
V1_4RESUME4[11:6]
V5_8FREEZE4[5:0]
V5_8FREEZE4[11:6]
V5_8RESUME4[5:0]
VTP5_8RESUME4[11:6]
VTP_SGLINEMODE
V1SPTR_SGLINE
V1INV_SGLINE
V2SPTR_SGLINE
V2INV_SGLINE
V3SPTR_SGLINE
V3INV_SGLINE
V4INV_SGLINE
Register Name
V4INVSECOND4
V1START_SGLINE[5:0]
V1START_SGLINE[11:6]
V2START_SGLINE[5:0]
V2START_SGLINE[11:6]
V3START_SGLINE[5:0]
V3START_SGLINE[11:6]
V4SPTR_SGLINE
V4START_SGLINE[5:0]
V4START_SGLINE[11:6]
–53–
V4 Sequence for Region #4 (Second Lines)
V4 and V7 Sequence Start for Region #4
V4 Sequence for Region #4 (Second Lines)
V4 and V8 Sequence Start for Region #4
V1 Second Sequence Inversion
V2 Second Sequence Inversion
V3 Second Sequence Inversion
V4 Second Sequence Inversion
Register Description
V4 Sequence Inversion for Region #4 (First Lines)
V4 Sequence Inversion for Region #4 (Second Lines)
V4 Sequence for Region #4 (First Lines)
V4 Sequence Inversion for Region #4 (First Lines)
V4 Sequence Inversion for Region #4 (Second Lines)
V1–V4 Freeze Start Position for Region #4
V1–V4 Resume Start Position for Region #4
V5–V8 Freeze Start Position for Region #4
V5–V8 Resume Start Position for Region #4
VTP Second Sequence Output Enable during SGLINE
V1 Second Sequence
V1 Start Position of Second V Pulse
V2 Second Sequence
V2 Start Position of Second V Pulse
V3 Second Sequence
V3 Start Position of Second VTP Pulse
V4 Second Sequence
V4 Start Position of Second VTP Pulse
AD9891/AD9895