AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 2

• Manufacturer Part Number: AD9891KBC
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9891KBC

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9891/AD9895
TABLE OF CONTENTS
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN CONFIGURATION-AD9891 . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS-AD9891 . . . . . . . . . . . 7
PIN CONFIGURATION-AD9895 . . . . . . . . . . . . . . . . . . . 8
PIN FUNCTION DESCRIPTIONS-AD9895 . . . . . . . . . . . 8
SPECIFICATION DEFINITIONS . . . . . . . . . . . . . . . . . . . 9
EQUIVALENT CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . 9
TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10
SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PRECISION TIMING HIGH SPEED TIMING
GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
HORIZONTAL CLAMPING AND BLANKING . . . . . . . . 15
VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . .17
DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 3
AD9891 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . 4
AD9895 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . 5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 6
PACKAGE THERMAL CHARACTERISTICS . . . . . . . . 6
Typical System Block Diagram . . . . . . . . . . . . . . . . . . . . 11
Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
High Speed Clock Programmability . . . . . . . . . . . . . . . . . .12
H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . .13
Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Individual CLPOB, CLPDM, and PBLK Sequences . . . . . 15
Individual HBLK Sequences . . . . . . . . . . . . . . . . . . . . . . .15
Horizontal Sequence Control . . . . . . . . . . . . . . . . . . . . . . .15
Individual Vertical Sequences . . . . . . . . . . . . . . . . . . . . . .18
Individual Vertical Regions . . . . . . . . . . . . . . . . . . . . . . . .19
Complete Field: Combining the Regions . . . . . . . . . . . . . . 20
Vertical Sequence Alteration . . . . . . . . . . . . . . . . . . . . . . .21
Second Vertical Sequence During VSG Lines . . . . . . . . . . 22
Vertical Sweep Mode Operation . . . . . . . . . . . . . . . . . . . .22
Vertical Multiplier Mode . . . . . . . . . . . . . . . . . . . . . . . . . .24
–2–
SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . . .26
ANALOG FRONT END DESCRIPTION AND
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
POWER-UP AND SYNCHRONIZATION . . . . . . . . . . . . 34
POWER-DOWN MODE OPERATION . . . . . . . . . . . . . . 35
HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . 37
VERTICAL TIMING EXAMPLE . . . . . . . . . . . . . . . . . . . 39
CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . .40
SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . .41
NOTES ON REGISTER LISTING . . . . . . . . . . . . . . . . . . 42
COMPLETE REGISTER LISTING . . . . . . . . . . . . . . . . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 57
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Frame Transfer CCD Mode . . . . . . . . . . . . . . . . . . . . . . 24
Vertical Sensor Gate (Shift Gate) Timing . . . . . . . . . . . . .25
Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . .26
Low Speed Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . .26
SUBCK Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Readout After Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . .27
VSUB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MSHUT and STROBE Control . . . . . . . . . . . . . . . . . . . .27
Example of Exposure and Readout of Interlaced Frame . . .29
DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 30
Input Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PxGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PxGA Color Steering Mode Timing . . . . . . . . . . . . . . . . 31
Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PxGA and VGA Gain Curves . . . . . . . . . . . . . . . . . . . . . 33
Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Recommended Power-Up Sequence for Master Mode . . . .34
SYNC During Master Mode Operation . . . . . . . . . . . . . . .35
Synchronization in Slave Mode . . . . . . . . . . . . . . . . . . . . .35
Notes About Accessing a Double-Wide Register . . . . . . . 41
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