AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 34

• Manufacturer Part Number: AD9891KBC
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9891KBC

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9891/AD9895
POWER-UP AND SYNCHRONIZATION
Recommended Power-Up Sequence for Master Mode
When the AD9891/AD9895 are powered up, the following
sequence is recommended (refer to Figure 42 for each step).
1. Turn on power supplies for the AD9891/AD9895.
2. Apply the master clock input CLI.
3. Reset and initialize the internal AD9891/AD9895 Registers.
4. Configure the AD9891/AD9895 for Master Mode timing by
6. Write a “1” to the PREVENTUPDATE Register
7. Write a “1” to the SYNCENABLE Register (Addr x024).
8. Write a “1” to the SYNCSUSPEND Register (Addr x026).
5. By default, the internal timing core is held in a reset state
(OUTPUT)
(OUTPUT)
OUTPUTS
DIGITAL
WRITES
(INPUT)
(INPUT)
SERIAL
(INPUT)
First, write a “1” to the SW_RESET Register (Addr x017)
followed by a “0” to the same register. Next, write
“110101” (53 decimal) to the INITIAL1 Register
(Addr x02B) followed by “000100” (4 decimal) to the
INTIAL2 Register (Addr x010). This sequence of writes
must always be done in the proper order:
writing a “1” to the MASTER Register (Addr x0EB).
with TGCORE_RSTB Register = “0.” Write a “1” to the
TGCORE_RSTB Register (Addr x029) to start the internal
timing core operation.
(Addr x01B). This will prevent any updating of the serial
register data.
This will allow the external SYNC to be used.
This will cause the outputs to be suspended during the
SYNC operation (see Figure 43).
SYNC
VDD
CLI
VD
HD
Addr x017
Addr x017
Addr x02B
Addr x010
Figure 42. Recommended Power-Up Sequence and Synchronization, Master Mode
t
PWR
H2/H4
H1/H3, RG, DCLK
Data 000001
Data 000000
Data 110101
Data 000100
–34–
10. If SYNC is HIGH at power-up, then bring SYNC input
11. Write a “1” to the OUT_CONT Register (Addr x018). This
12. Write a “0” to the PREVENTUPDATE Register
13. Bring SYNC back HIGH. This will cause the internal
SYNC During Master Mode Operation
The SYNC input may be used any time during operation to
resync the AD9891/AD9895 counters with external timing, as
shown in Figure 43. The operation of the digital outputs may
be suspended during the SYNC operation by setting the
SYNCSUSPEND Register (Addr x026) to a “1.”
Synchronization in Slave Mode
When the AD9891/AD9895 is used in Slave Mode, the VD and
HD inputs are used to synchronize the internal counters. Fol-
lowing a falling edge of VD, there will be a latency of eight
master clock cycles (CLI) after the falling edge of HD until the
internal H-counter will be reset. The reset operation is shown in
Figure 44.
9. Write to desired registers to configure high speed timing,
horizontal timing, vertical timing, and shutter timing.
LOW. Also, SYNC may be held low from power-up.
will allow the outputs to become active after SYNC rising edge.
(Addr x01B). This will allow the serial information to be up-
dated at the next VD/HD falling edge.
counters to reset to “0” and start VD/HD operation.
VD/HD edge allows register updates to occur, including
OUT_CONT, which enables all clock outputs.
1 H
ODD FIELD
CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS
UPDATED AT VD/HD EDGE
1 V
EVEN FIELD
REV. A