AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 16

• Manufacturer Part Number: AD9891KBC
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9891KBC

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9891/AD9895
zontal sequences. Up to four SCPs are available to divide the
readout into four separate regions, as shown in Figure 16. The
SCP0 is always hard-coded to line 0, and SCP1–SCP3 are
register programmable. During each region bound by the SCP,
the SPTR Registers designate which sequence is used by each
signal. CLPOB and CLPDM share the same SCP, PBLK has a
separate set of SCP, and HBLK shares the vertical RCP (see
Vertical Timing Generation section). For example,
Register
SPOL
TOG1
TOG2
Register
HBLKMASK
HBLKTOG1
HBLKTOG2
Register
SCP1–SCP3
SPTR0–SPTR3 2b
Register
VTPRCP1–
VTPRCP7
HBLKSPTR0–
HBLKSPTR7
Length
1b
12b
12b
Length
1b
12b
12b
Length
12b
Length
12b
2b
Table V. Horizontal Sequence Control Parameters for CLPOB, CLPDM, and PBLK
SEQUENCE CHANGE POSITION #0
SEQUENCE CHANGE POSITION #1
SEQUENCE CHANGE POSITION #2
SEQUENCE CHANGE POSITION #3
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITH-
IN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
Table III. CLPOB, CLPDM, and PBLK Individual Sequence Parameters
Range
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Range
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Range
0–4095 Line Number
0–3 Sequence Number
Range
0–4095 Line Number
0–3 Sequence Number
Table VI. Horizontal Sequence Control Parameters for HBLK
Figure 16. Clamp and Blanking Sequence Flexibility
(V-COUNTER = 0)
Table IV. HBLK Individual Sequence Parameters
SINGLE FIELD (1 VD INTERVAL)
Description
Starting Polarity of Vertical Transfer Pulse for Sequences 0–3
First Toggle Position within Line for Sequences 0–3
Second Toggle Position within Line for Sequences 0–3
Description
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)
First Toggle Position within Line for Sequences 0–3
Second Toggle Position within Line for Sequences 0–3
Description
CLPOB/PBLK SCP to Define Horizontal Regions 0–3
Sequence Pointer for Horizontal Regions 0–3
Description
Vertical Region Change Positions (See Table IX.)
Sequence Pointer for HBLK Regions 0–7
–16–
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 3
CLAMP AND PBLK SEQUENCE REGION 4
CLAMP AND PBLK SEQUENCE REGION 1
CLPSCP1 will define Region 0 for CLPOB and CLPDM,
and in that region any of the four individual CLPOB and
CLPDM sequences may be selected with the SPTR Registers.
The next SCP defines a new region, and in that region each
signal can be assigned to a different individual sequence. Be-
cause HBLK shares the vertical RCP, there are up to eight
regions where HBLK sequences may be changed using the eight
HBLKSPTR Registers.
REV. A