AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 24

• Manufacturer Part Number: AD9891KBC
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9891KBC

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9891/AD9895
Vertical Multiplier Mode
To generate very wide vertical timing pulses, a vertical region may
be configured into Multiplier Mode. This mode uses the vertical
sequence registers in a slightly different manner. Multiplier Mode
can be used to support unusual CCD timing requirements, such as
vertical pulses that are wider than a single HD line length.
The start polarity and toggle positions are still used in the same
manner as the standard sequence generation, but the length is
used differently. Instead of using the pixel counter (HD counter)
to specify the toggle position locations (VTPTOG1, 2, 3) of the
sequence, VTP length (VTPLEN) is multiplied by the
VTPTOG position to allow very long sequences to be generated.
To calculate the exact toggle position, counted in pixels after the
start position:
Because the VTPTOG Register is multiplied by VTPLEN, the
resolution of the toggle position placement is reduced. If
VTPLEN = 4, the toggle position accuracy is now reduced to
4-pixel steps instead of single pixel steps. Table XII summarizes
how the Individual Vertical Sequence Registers are pro-
grammed for Multiplier Mode operation. Note that the bit
ranges for the VTPTOG and VTPREP Registers differ from the
normal operation shown in Table VII. In Multiplier Mode, the
VTPREP Register should always be programmed to the same
value as the highest toggle position register.
Register
MULTI
VTPPOL
VTPTOG1
VTPTOG2
VTPTOG3
VTPLEN
VTPREP
Multiplier Toggle Position VTPTOG VTPLEN
MULTIPLIER MODE VERTICAL SEQUENCE PROPERTIES:
1: START POLARITY (ABOVE: STARTPOL = 0)
2: 1ST, 2ND, AND 3RD TOGGLE POSITIONS (ABOVE: VTPTOG1 = 2, VTPTOG2 = 9)
3: LENGTH OF VTP COUNTER (ABOVE: VTPLEN = 4). THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4: TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTPTOG
5: ENABLE SWEEP REGION ALLOWS THE COUNTERS TO CROSS THE HD BOUNDARIES
VTPLEN
PIXELS
V1–V4
HD
Length
1b
1b
12b
12b
12b
10b
12b
1
1
1
2
2
3
3
START POSITION OF SEQUENCE IS INDIVIDUALLY PROGRAMMABLE FOR EACH V1–V4 OUTPUT
3
Figure 27. Example of Multiplier Region for Wide Vertical Pulse Timing
4 1
4 5
Range
HIGH/LOW
HIGH/LOW
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–1023 Pixels
0–4096
=
Table XII. Multiplier Mode and Sequence Register Parameters
2
6
3
7
4
8
4
2
1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
2
×
3
4
1
2
3
Description
High Enables Multiplier Mode for Each Region 0–4
Starting Polarity of Vertical Transfer Pulse for Each Sequence 0–11
First Toggle Position for Each Sequence 0–11
Second Toggle Position for Each Sequence 0–11
Third Toggle Position for Each Sequence 0–7
“Multiplier” Factor for Repetition Counter
Should Be Programmed to the Same Value as the Highest Toggle Position
4
5
VTPLEN)
1
–24–
2
3
The example shown in Figure 27 illustrates this operation. The
first toggle position is 2 and the second toggle position is 9. In
Nonmultiplier Mode, this would cause the V-sequence to
toggle at pixel 2 and then pixel 9 within a single HD line. How-
ever, now toggle positions are multiplied by the VTPLEN = 4,
so the first toggle occurs at pixel count = 8, and the second toggle
occurs at pixel count = 36. Sweep Mode should be enabled to
allow the toggle positions to cross the HD line boundaries.
Frame Transfer CCD Mode
The AD9891/AD9895 may also be configured for use with frame
transfer CCDs. In Frame Transfer CCD (FTCCD) Mode,
an additional four vertical outputs are available for a total of
eight outputs (V1–V8). In this case, V1–V4 are used for clock-
ing the active image area, and V5–V8 are used for clocking the
storage area. In FTCCD Mode, the sequences assigned to the
V1–V4 outputs are duplicated at the V5–V8 outputs to allow the
storage area to be clocked along with the image area. Individual
masking of the V1–V4 and V5–V8 outputs allows for vertical
decimation techniques during transfer from the image to the
storage area. The additional outputs V5–V8 are available on four
of the sensor gate output pins, VSG1–VSG4. Figure 28 shows
an example of the eight V-clocks configured for use with a frame
transfer CCD.
4
1
2
3
4
1
2
3
4 1
2
3
4 1
5
2
3
4 1
2
4
2
3
4
REV. A