AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 31

• Manufacturer Part Number: AD9891KBC
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9891KBC

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

example, the Mosaic Separate Steering Mode accommodates the
popular “Bayer” arrangement of Red, Green, and Blue filters
(see Figure 38a).
The same Bayer pattern can also be interlaced, and the Mosaic
Interlaced Mode should be used with this type of CCD (see
Figure 38b). The color steering performs the proper multiplex-
ing of the R, G, and B gain values (loaded into the PxGA gain
registers) and is synchronized by the vertical (VD) and horizon-
tal (HD) sync pulses. The PxGA gain for each of the four
channels is variable from –2 dB to +10 dB, controlled in 64
steps through the serial interface. The PxGA gain curve is
shown in Figure 40.
REV. A
CDS
SHP/SHD
PxGA GAIN
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “0101” AND “2323” LINES.
3. FLD STATUS IS IGNORED.
REGISTER
PxGA GAIN
NOTES
1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.
2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “2323” LINE.
3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER “0” (FLD = ODD) OR “2” (FLD = EVEN).
REGISTER
HD
VD
FLD
HD
VD
FLD
HD
VD
6
PxGA
Figure 37. PxGA Block Diagram
X
X
STEERING
CONTROL
X
COLOR
2
MUX
X
4:1
VGA
0
0
1
1
3
0
GAIN0
GAIN1
GAIN2
GAIN3
0
1
SELECTION
STEERING
1
Figure 39b. Mosaic Interlaced Color Steering Mode
Figure 39a. Mosaic Separate Color Steering Mode
MODE
REGISTERS
PxGA
PxGA GAIN
2
0
ODD FIELD
3
ODD FIELD
1
2
0
CONTROL
REGISTER
BITS D0:D2
3
1
0
0
1
1
0
–31–
0
1
1
Figure 38a. CCD Color Filter Example: Progressive Scan
CCD: PROGRESSIVE BAYER
CCD: INTERLACED BAYER
Figure 38b. CCD Color Filter Example: Interlaced
0
EVEN FIELD
ODD FIELD
2
Gb
Gb
Gb
Gb
Gb
Gb
R
R
R
R
R
R
1
3
Gr
Gr
Gr
Gr
Gr
Gr
B
B
B
B
B
B
0
2
Gb
Gb
Gb
Gb
Gb
Gb
R
R
R
R
R
R
1
3
Gr
Gr
Gr
Gr
B
B
B
B
Gr
Gr
2
B
B
2
LINE0
LINE1
LINE2
LINE0
LINE1
LINE2
LINE0
LINE1
LINE2
3
EVEN FIELD
EVEN FIELD
3
2
2
MOSAIC SEPARATE COLOR
STEERING MODE
3
MOSAIC INTERLACED
COLOR STEERING MODE
AD9891/AD9895
GAIN0, GAIN1, GAIN0, GAIN1, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
3
0
2
1
3
0
2
1
3
0
0