IC MUX/DEMUX 2X1 8TSSOP

74LVC2G53DP,125

Manufacturer Part Number74LVC2G53DP,125
DescriptionIC MUX/DEMUX 2X1 8TSSOP
ManufacturerNXP Semiconductors
Series74LVC
TypeAnalog Multiplexer
74LVC2G53DP,125 datasheet
 

Specifications of 74LVC2G53DP,125

Package / Case8-TSSOPFunctionMultiplexer/Demultiplexer
Circuit1 x 2:1On-state Resistance6 Ohm
Voltage Supply SourceSingle SupplyVoltage - Supply, Single/dual (±)1.65 V ~ 5.5 V
Current - Supply0.1µAOperating Temperature-40°C ~ 125°C
Mounting TypeSurface MountNumber Of Channels1 Channel
On Resistance (max)34 Ohm (Typ) @ 1.95 VOn Time (max)6.7 ns (Typ) @ 1.95 V
Off Time (max)6.8 ns (Typ) @ 1.95 VSupply Voltage (max)5.5 V
Supply Voltage (min)1.65 VMaximum Power Dissipation250 mW
Maximum Operating Temperature+ 125 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTNumber Of SwitchesSingle
Switch Current (typ)0.0001 mA @ 5.5 VPackage8TSSOP
Maximum On Resistance195@1.95V OhmMaximum Propagation Delay Bus To Bus2.5@1.95V@-40C to 125C|1.5@2.7V@-40C to 125C|1@3.6V@-40C to 125C|0.8@5.5V@-40C to 125C ns
Maximum Low Level Output Current50 mAMultiplexer Architecture2:1
Maximum Turn-off Time6.8(Typ)@1.95V nsMaximum Turn-on Time6.7(Typ)@1.95V ns
Power Supply TypeSingleLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names74LVC2G53DP-G
74LVC2G53DP-G
935280383125
  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Page 1/28

Download datasheet (647Kb)Embed
Next
74LVC2G53
2-channel analog multiplexer/demultiplexer
Rev. 6 — 27 September 2010
1. General description
The 74LVC2G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device.
The 74LVC2G53 provides one analog multiplexer/demultiplexer with a digital select
input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an
active LOW enable input (E). When pin E is HIGH, the switch is turned off.
Schmitt-trigger action at the select and enable inputs makes the circuit tolerant of slower
input rise and fall times across the entire V
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 Ω (typical) at V
6.5 Ω (typical) at V
6 Ω (typical) at V
Switch current capability of 32 mA
High noise immunity
CMOS low-power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD 78 Class I
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Control inputs accepts voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
range from 1.65 V to 5.5 V.
CC
= 2.7 V
CC
= 3.3 V
CC
= 5 V
CC
Product data sheet

74LVC2G53DP,125 Summary of contents

  • Page 1

    Rev. 6 — 27 September 2010 1. General description The 74LVC2G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC2G53 provides one analog multiplexer/demultiplexer with a digital select input (S), two independent inputs/outputs (Y0 and ...

  • Page 2

    ... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVC2G53DP −40 °C to +125 °C 74LVC2G53DC −40 °C to +125 °C 74LVC2G53GT −40 °C to +125 °C 74LVC2G53GF −40 °C to +125 °C 74LVC2G53GD −40 °C to +125 °C 74LVC2G53GM −40 °C to +125 °C 74LVC2G53GN − ...

  • Page 3

    ... NXP Semiconductors Fig 2. Logic diagram 6. Pinning information 6.1 Pinning 74LVC2G53 GND 3 GND 4 001aae798 Fig 3. Pin configuration SOT505-2 and SOT765-1 74LVC2G53 Product data sheet Fig 4. All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 September 2010 74LVC2G53 2-channel analog multiplexer/demultiplexer Z 001aad387 ...

  • Page 4

    ... NXP Semiconductors 74LVC2G53 GND 3 GND 4 Transparent top view Fig 5. Pin configuration SOT996-2 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 GND 3 GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. ...

  • Page 5

    ... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current IK I switch clamping current SK V switch voltage SW I switch current ...

  • Page 6

    ... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions V HIGH-level input voltage LOW-level input voltage input leakage pin S and pin E; I current GND; ...

  • Page 7

    ... NXP Semiconductors 10.1 Test circuits GND GND Fig 7. Test circuit for measuring OFF-state leakage current GND and V = open circuit Fig 8. Test circuit for measuring ON-state leakage current 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see ...

  • Page 8

    ... NXP Semiconductors Table 8. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Symbol Parameter R ON resistance (rail) ON(rail resistance ON(flat) (flatness) [1] Typical values are measured at T [2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical V temperature ...

  • Page 9

    ... NXP Semiconductors ( Fig 10. Typical ON resistance as a function of input voltage (Ω (4) (3) (2) ( 0.4 0.8 = 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 11. ON resistance as a function of input voltage 1 74LVC2G53 Product data sheet (Ω) ...

  • Page 10

    ... NXP Semiconductors (Ω) 11 (1) 9 (2) ( 0.5 1.0 1.5 = 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 13. ON resistance as a function of input voltage 2 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. ...

  • Page 11

    ... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay see enable time Yn; see Yn; see disable time Yn; see dis Yn; see [1] Typical values are measured the same as t and t ...

  • Page 12

    ... NXP Semiconductors 11.1 Waveforms and test circuits Measurement points are given in Logic levels: V and Fig 16. Input ( output (Z or Yn) propagation delays S, E input output Z, Yn LOW to OFF OFF to LOW output Z, Yn HIGH to OFF OFF to HIGH Measurement points are given in Logic levels: V and V ...

  • Page 13

    ... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistor Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 18. Test circuit for measuring switching times Table 11. Test data ...

  • Page 14

    ... NXP Semiconductors 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T Symbol Parameter THD total harmonic distortion −3 dB frequency response R f (−3dB) α isolation (OFF-state) iso Q charge injection inj 11.3 Test circuits Fig 19. Test circuit for measuring total harmonic distortion ...

  • Page 15

    ... NXP Semiconductors Adjust f voltage to obtain 0 dBm level at output. Increase f i Fig 20. Test circuit for measuring the frequency response when switch is in ON-state Adjust f voltage to obtain 0 dBm level at input. i Fig 21. Test circuit for measuring isolation (OFF-state) 74LVC2G53 Product data sheet switch 0.1 μF ...

  • Page 16

    ... NXP Semiconductors a. Test circuit b. Input and output pulse definitions = ΔV × inj O L ΔV = output voltage variation generator resistance. gen V = generator voltage. gen Fig 22. Test circuit for measuring charge injection 74LVC2G53 Product data sheet logic (S) off on input V O All information provided in this document is subject to legal disclaimers. ...

  • Page 17

    ... NXP Semiconductors 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

  • Page 18

    ... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 19

    ... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

  • Page 20

    ... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

  • Page 21

    ... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 27. Package outline SOT996-2 (XSON8U) ...

  • Page 22

    ... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

  • Page 23

    ... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

  • Page 24

    ... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

  • Page 25

    ... NXP Semiconductors 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model CDM Charged Device Model DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date 74LVC2G53 v.6 20100927 • ...

  • Page 26

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 27

    ... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC2G53 Product data sheet 15 ...

  • Page 28

    ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics 10.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 ...