M28W320FCT70ZB6E Micron Technology Inc, M28W320FCT70ZB6E Datasheet - Page 16

• Manufacturer Part Number: M28W320FCT70ZB6E
• Manufacturer: Micron Technology Inc

Specifications of M28W320FCT70ZB6E

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 47
• Lead Free Status / Rohs Status: Compliant

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4.1
4.2
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Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. An internal
Program/Erase Controller handles all timings and verifies the correct execution of the
Program and Erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time during, to monitor the progress of the operation, or
the Program/Erase states. See
and see
Command Interface.
The Command Interface is reset to Read mode when power is first applied, when exiting
from Reset or whenever V
exactly. Any invalid combination of commands will reset the device to Read mode. Refer to
Table 4:
Read Memory Array command
The Read command returns the memory to its Read mode. One Bus Write cycle is required
to issue the Read Memory Array command and return the memory to Read mode.
Subsequent read operations will read the addressed location and output the data. When a
device Reset occurs, the memory defaults to Read mode.
Read Status Register command
The Status Register indicates when a program or erase operation is complete and the
success or failure of the operation itself. Issue a Read Status Register command to read the
Status Register’s contents. Subsequent Bus Read operations read the Status Register at
any address, until another command is issued. See
details on the definitions of the bits.
The Read Status Register command may be issued at any time, even during a
Program/Erase operation. Any Read attempt during a Program/Erase operation will
automatically output the content of the Status Register.
Appendix
Commands, in conjunction with the text descriptions below.
D, and
Table
DD
is lower than V
Table 3: Command
32, Write State Machine Current/Next, for a summary of the
LKO
. Command sequences must be followed
Codes, for a summary of the commands
Table 11: Status Register
Bits, for