M28W320FCT70ZB6E Micron Technology Inc, M28W320FCT70ZB6E Datasheet - Page 18

• Manufacturer Part Number: M28W320FCT70ZB6E
• Manufacturer: Micron Technology Inc

Specifications of M28W320FCT70ZB6E

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 47
• Lead Free Status / Rohs Status: Compliant

4.5
4.6
18/69
Block Erase command
The Block Erase command can be used to erase a block. It sets all the bits within the
selected block to ’1’. All previous data in the block is lost. If the block is protected then the
Erase operation will abort, the data in the block will not be changed and the Status Register
will output the error.
Two Bus Write cycles are required to issue the command.
1.
2.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are
set and the command aborts.
Erase aborts if Reset turns to V
operation is aborted, the block must be erased again.
During Erase operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command, all other commands will be ignored. Typical Erase
times are given in
See
for using the Erase command.
Program command
The memory array can be programmed word-by-word. Two bus write cycles are required to
issue the Program Command.
1.
2.
During Program operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command. Typical Program times are given in
Program, Erase Times and Program/Erase Endurance
Programming aborts if Reset goes to V
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See
using the Program command.
Appendix
Appendix
The first bus cycle sets up the Erase command.
The second latches the block address in the internal state machine and starts the
Program/Erase Controller.
The first bus cycle sets up the Program command.
The second latches the Address and the Data to be written and starts the
Program/Erase Controller.
C,
C,
Figure 20: Erase Flowchart and Pseudo
Figure 16: Program Flowchart and Pseudo
Table 8: Program, Erase Times and Program/Erase Endurance
IL
. As data integrity cannot be guaranteed when the Erase
IL
. As data integrity cannot be guaranteed when the
Cycles.
Code, for a suggested flowchart
Code, for the flowchart for
Table 8:
Cycles.