LFXP3E-4TN144C Lattice, LFXP3E-4TN144C Datasheet - Page 248

• Manufacturer Part Number: LFXP3E-4TN144C
• Description: IC FPGA 3.1KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Appendix D. Generic (Non-Memory) High-Speed DDR Interface
The following HDL implements the DDR input interface using PFU registers for non-memory DDR applications.
VHDL Implementation
library IEEE;
use IEEE.std_logic_1164.all;
library ec;
use ec.components.all;
entity ddrin is
end ddrin;
architecture structure of ddrin is
-- parameterized module component declaration
component pll90
end component;
attribute syn_useioff : boolean;
attribute syn_useioff of structure : architecture is false;
begin
demux: process (rst, ddrclk90)
begin
port (rst : in std_logic;
port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic;
ddrclk: in std_logic;
ddrdata: in std_logic_vector(7 downto 0);
datap: out std_logic_vector(7 downto 0);
datan: out std_logic_vector(7 downto 0));
-- parameterized module component instance
signal pos0 : std_logic_vector( 7 downto 0 );
signal pos1 : std_logic_vector( 7 downto 0 );
signal neg0 : std_logic_vector( 7 downto 0 );
signal clklock : std_logic;
signal ddrclk0: std_logic;
signal ddrclk90: std_logic;
signal vcc_net : std_logic;
signal gnd_net: std_logic;
vcc_net <= '1';
gnd_net <= '0';
I0 : pll90
port map (CLK=>ddrclk, RESET=>rst, CLKOP=>ddrclk0, CLKOS=>ddrclk90, LOCK=>clklock);
if
elsif rising_edge(ddrclk90) then
CLKOS: out std_logic; LOCK: out std_logic);
rst = '1' then
pos0
neg0
pos1
pos0
<= (others => '0');
<= (others => '0');
<= (others => '0');
<= ddrdata;
10-29
LatticeECP/EC and LatticeXP
DDR Usage Guide