LFXP3E-4TN144C Lattice, LFXP3E-4TN144C Datasheet - Page 4

• Manufacturer Part Number: LFXP3E-4TN144C
• Description: IC FPGA 3.1KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
sysIO Standards Supported in Each Bank......................................................................................................... 8-5
LVCMOS Buffer Configurations ......................................................................................................................... 8-5
Differential SSTL and HSTL Support ................................................................................................................. 8-7
PCI Support with Programmable PCICLAMP .................................................................................................... 8-7
5V Interface with PCI Clamp Diode.................................................................................................................... 8-8
Programmable Input Delay ................................................................................................................................ 8-9
Software sysIO Attributes................................................................................................................................... 8-9
Design Considerations and Usage................................................................................................................... 8-12
Differential I/O Implementation......................................................................................................................... 8-13
Technical Support Assistance.......................................................................................................................... 8-13
Appendix A. HDL Attributes for Synplify
VHDL Synplify/Precision RTL Synthesis.......................................................................................................... 8-15
Verilog for Synplify ........................................................................................................................................... 8-18
Verilog for Precision RTL Synthesis................................................................................................................. 8-20
Appendix B. sysIO Attributes Using Preference Editor User Interface............................................................. 8-22
Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-23
V
V
Input Reference Voltage (V
V
Mixed Voltage Support in a Bank.............................................................................................................. 8-4
Programmable Pull-up/Pull-Down/Buskeeper........................................................................................... 8-5
Programmable Drive ................................................................................................................................. 8-5
Programmable Slew Rate ......................................................................................................................... 8-7
Open Drain Control ................................................................................................................................... 8-7
IO_TYPE ................................................................................................................................................... 8-9
OPENDRAIN........................................................................................................................................... 8-10
DRIVE ..................................................................................................................................................... 8-10
PULLMODE ............................................................................................................................................ 8-11
PCICLAMP.............................................................................................................................................. 8-11
SLEWRATE ............................................................................................................................................ 8-11
FIXEDDELAY.......................................................................................................................................... 8-11
DIN/DOUT............................................................................................................................................... 8-11
LOC......................................................................................................................................................... 8-12
Banking Rules ......................................................................................................................................... 8-12
Differential I/O Rules ............................................................................................................................... 8-12
Assigning V
LVDS....................................................................................................................................................... 8-13
BLVDS .................................................................................................................................................... 8-13
RSDS ...................................................................................................................................................... 8-13
LVPECL .................................................................................................................................................. 8-13
Differential SSTL and HSTL.................................................................................................................... 8-13
Syntax ..................................................................................................................................................... 8-15
Examples ................................................................................................................................................ 8-15
Syntax ..................................................................................................................................................... 8-18
Examples ................................................................................................................................................ 8-18
Syntax ..................................................................................................................................................... 8-20
Example .................................................................................................................................................. 8-20
IOBUF ..................................................................................................................................................... 8-23
LOCATE.................................................................................................................................................. 8-23
USE DIN CELL........................................................................................................................................ 8-24
USE DOUT CELL.................................................................................................................................... 8-24
PGROUP VREF ...................................................................................................................................... 8-24
CCAUX
CCJ
REF1
(1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 8-3
for DDR Memory Interface ............................................................................................................. 8-3
(3.3V) ........................................................................................................................................... 8-3
REF
/ V
REF
Groups for Referenced Inputs............................................................................. 8-12
REF1,
V
®
REF2
and Precision
)................................................................................................... 8-3
3
®
RTL Synthesis ........................................................ 8-15
LatticeXP Family Handbook
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