LFXP3E-4TN144C Lattice, LFXP3E-4TN144C Datasheet - Page 303

• Manufacturer Part Number: LFXP3E-4TN144C
• Description: IC FPGA 3.1KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
During SRAM configuration from an external device INITN going low indicates that the SRAM is being initialized;
INITN going high indicates that the FPGA is ready to accept configuration data. To delay configuration the INITN
pin can be held low externally. The device will not enter configuration mode as long as the INITN pin is held low.
After configuration has started INITN is used to indicate a bitstream error. The INITN pin will be driven low if the
calculated CRC and the configuration data CRC do not match; DONE will then remain low and the LatticeXP will
not wake up.
During SRAM configuration from on-chip Flash INITN is not used or monitored and is driven low.
When programming on-chip Flash the INITN pin is only used to indicate an error during erase or program. If an
error occurs INITN will be driven low. During Flash Direct programming an error will prevent the FPGA from config-
uring from the Flash, during Flash Background programming an error will not affect the configuration already run-
ning in SRAM.
DONE
The DONE pin is a dedicated bi-directional open drain with a weak pull-up (default), or an actively driven pin.
DONE will be driven low when the device is in configuration mode and the internal DONE bit is not programmed.
When the INITN and PROGRAMN pins go high (or in the case of SDM just PROGRAMN goes high), and the inter-
nal DONE bit is programmed, the DONE pin will be released (or driven high, if it is an actively driven pin). The
DONE pin can be held low externally and, depending on the wake-up sequence selected, the device will not
become functional until the DONE pin is externally brought high.
Reading the DONE bit is a good way for an external device to tell if the FPGA is configured.
When using JTAG to configure SRAM the DONE pin is driven by the boundary scan cell, so the state of the DONE
pin has no meaning during JTAG configuration.
CCLK
CCLK is a dedicated bi-directional pin; direction depends on whether a Master or Slave mode is selected. If a Mas-
ter mode is selected via the CFG pins, the CCLK pin will become an output pin; otherwise CCLK is an input pin.
If the CCLK pin becomes an output, the internal programmable oscillator is connected to the CCLK and is driven
out to slave devices. CCLK will stop 120 clock cycles after the DONE pin is brought high and the device wake-up
sequence completed. The extra clock cycles ensure that enough clocks are provided to wake-up other devices in
the chain. When stopped, CCLK becomes an input (tri-stated output). CCLK will restart (become an output) on the
next configuration initialization sequence.
The MCCLK_FREQ parameter (see ispLEVER software documentation) controls the CCLK master frequency (see
Table 13-3). Until changed during configuration CCLK will be 2.5 MHz. One of the first things loaded during config-
uration is the MCCLK_FREQ parameter; once this parameter is loaded the frequency changes to the selected
value using a glitchless switch. Care should be exercised not to exceed the frequency specification of the slave
devices or the signal integrity capabilities of the PCB layout.
Table 13-3. Master Clock Frequency Selections
Note: Default is the lowest frequency, 2.5 MHz.
CCLK (MHz)
10.0
2.5
4.3
5.4
6.9
8.1
9.2
CCLK (MHz)
13-4
13
15
20
26
30
34
41
LatticeXP sysCONFIG Usage Guide
CCLK (MHz)
130
45
51
55
60
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