LFXP3E-4TN144C Lattice, LFXP3E-4TN144C Datasheet - Page 357

• Manufacturer Part Number: LFXP3E-4TN144C
• Description: IC FPGA 3.1KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Clock boosting is typically most useful in designs that are only missing timing on a few paths for one or two prefer-
ences. If the design is missing timing by over a few nanoseconds on any given path, clock boosting will not be able
to schedule skew in a way that will eliminate enough timing to make the critical preference. Clock boosting run
times can be shortened by using a preference file with only the failing preferences in it.
Figure 17-11. Clock Boosting Example
The example illustrated in Figure 17-11 shows two register-to-register transfers that both need to meet the 10 ns
period constraint. By using delay cell DEL2 to delay the clock input on flip-flop FF_2, the first register transfer will
make its period constraint with a new minimum period of ~9.7 ns and the second register transfer will make its
period constraint by ~8.3 ns.
The D1, D2, and D3 delays shown in Figure 17-11 are variable depending on the speed grade and Lattice Semi-
conductor FPGA device family. For complete timing information, reference the software generated timing data
sheet, included with ispLEVER, for the desired Lattice Semiconductor FPGA device family.
To Perform Clock Boosting in the Project Navigator
As shown in Figure 17-12, the original .ncd and .prf files as well as the output .ncd file are typed into the corre-
sponding entries. Checking “Maximize Frequency” will push the tool to improve the frequency beyond the input
preference requirement. This is generally only useful for bench marking.
1. In the Project Navigator Sources window, select the target device.
2. In the Processes window, right-click the Clock Boosting under Place & Route Design process, and then
3. Select the Clock Boosting Output Filename property from the property list and type the name of the out-
4. Click Close to close the dialog box.
select Properties to open the Properties dialog box.
put file name in the edit region (<file_name>.ncd).
Target Performance: 10 ns period (100 MHz)
Clock
FF_1
DEL1 ~= 0.7 ns
DEL2 ~= 1.3 ns
DEL3 ~= 2.0 ns
DEL
DEL
DEL
11 ns
1
2
3
Combinational
17-13
Logic
FF_2
7 ns
Lattice Semiconductor FPGA
Successful Place and Route
FF_3