LFXP3E-4TN144C Lattice, LFXP3E-4TN144C Datasheet - Page 9

• Manufacturer Part Number: LFXP3E-4TN144C
• Description: IC FPGA 3.1KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Board Timing Guidelines for the DDR SDRAM Controller IP Core
PCB Layout Recommendations for BGA Packages
Section III. LatticeXP Family Handbook Revision History
ispLEVER Controlled Place and Route.......................................................................................................... 17-10
Guided Map and PAR .................................................................................................................................... 17-14
Conclusion ..................................................................................................................................................... 17-15
Technical Support Assistance........................................................................................................................ 17-16
Introduction ...................................................................................................................................................... 18-1
Read Operation................................................................................................................................................ 18-2
Write Operation ................................................................................................................................................ 18-4
Address and Command Signals....................................................................................................................... 18-5
Board Design Guidelines ................................................................................................................................. 18-7
Technical Support Assistance.......................................................................................................................... 18-8
Appendix A. Example Extractions of Delays from Timing Reports .................................................................. 18-9
Introduction ...................................................................................................................................................... 19-1
BGA Breakout and Routing Examples ............................................................................................................. 19-1
PCB Fabrication Cost and Design Rule Considerations ................................................................................ 19-12
Advantages and Disadvantages of BGA Packaging ...................................................................................... 19-13
BGA Package Test and Assembly ................................................................................................................. 19-14
PCB Design Support ...................................................................................................................................... 19-17
Technical Support Assistance........................................................................................................................ 19-17
Revision History ............................................................................................................................................. 19-18
Revision History ............................................................................................................................................... 20-1
Running Multiple Routing Passes ......................................................................................................... 17-10
Using Multiple Placement Iterations (Cost Tables) ............................................................................... 17-11
Clock Boosting ...................................................................................................................................... 17-12
Notes on Guided Mapping .................................................................................................................... 17-15
Notes on Guided PAR........................................................................................................................... 17-15
Set-up Time Calculation for the Data Input (Max. Case) ........................................................................ 18-3
Hold Time Calculation for the Data Input (Min. Case)............................................................................. 18-3
Write Set-up ............................................................................................................................................ 18-4
Write Hold ............................................................................................................................................... 18-5
Set-up Calculation................................................................................................................................... 18-6
Hold Calculation ...................................................................................................................................... 18-7
64-ball csBGA BGA Breakout and Routing Example.............................................................................. 19-3
64-ball ucBGA BGA Breakout and Routing Example.............................................................................. 19-4
100-ball csBGA BGA Breakout and Routing Examples .......................................................................... 19-5
132-ball csBGA BGA Breakout Examples .............................................................................................. 19-7
144-ball csBGA BGA Breakout Examples .............................................................................................. 19-9
256-ball caBGA BGA Breakout Examples ............................................................................................ 19-11
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LatticeXP Family Handbook
Table of Contents