LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 243

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Appendix C. VHDL Example for DDR Input and Output Modules
library IEEE;
use IEEE.std_logic_1164.all;
library ec;
use ec.components.all;
entity ddr_mem is
--*****DDR interface signals assigned SSTL25 IO Standard *************
ATTRIBUTE IO_TYPE
ATTRIBUTE IO_TYPE OF ddrclk
ATTRIBUTE IO_TYPE OF dq
ATTRIBUTE IO_TYPE OF dqs
end ddr_mem;
architecture structure of ddr_mem is
--*****DDR Input register*********************************************
component IDDRXB
end component;
port(
D
ECLK : in STD_LOGIC;
SCLK : in STD_LOGIC;
CE
LSR
DDRCLKPOL
QA
QB
port( dq
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC;
: out STD_LOGIC);
dqs
clk
clk90
reset
uddcntl
read
dataout_p : in std_logic_vector(7 downto 0);
dataout_n : in std_logic_vector(7 downto 0);
datatri_p : in std_logic_vector(7 downto 0);
datatri_n : in std_logic_vector(7 downto 0);
dqstri_p
dqstri_n
ddrclk
datain_p
datain_n
dqsc
prmbdet
lock
ddrclkpol : out std_logic);
: in STD_LOGIC;
: inout std_logic_vector(7 downto 0 );
: inout std_logic;
: in std_logic; -- core clock
: in std_logic; -- 90 degree phase shifted clock from the pll
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic;
: out std_logic_vector(7 downto 0);
: out std_logic_vector(7 downto 0);
: out std_logic;
: out std_logic;
: out std_logic;
: string;
: SIGNAL IS "SSTL25D_II";
: SIGNAL IS "SSTL25_II";
: SIGNAL IS "SSTL25_II";
10-24
LatticeECP/EC and LatticeXP
DDR Usage Guide