LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 69

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

www.latticesemi.com
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
November 2007
Signal Descriptions
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
GSRN
NC
GND
V
V
V
V
GNDP0
GNDP1
V
V
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_PLL[T, C]_IN_A
[LOC][num]_PLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
[LOC]DQS[num]
CC
CCAUX
CCP0
CCP1
CCIOx
REF1(x),
V
REF2(x)
Signal Name
I/O
I/O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
Some of these user programmable pins are shared with special function pins.
These pin when not used as special purpose pins can be programmed as I/
Os for user logic.
During configuration, the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
configuration.
Global RESET signal. (Active low). Any I/O pin can be configured to be
GSRN.
No connect.
GND - Ground. Dedicated Pins.
VCC - The power supply pins for core logic. Dedicated Pins.
V
erenced input buffers. Dedicated Pins.
Voltage supply pins for ULM0PLL (and LLM1PLL
Voltage supply pins for URM0PLL (and LRM1PLL
Ground pins for ULM0PLL (and LLM1PLL
Ground pins for URM0PLL (and LRM1PLL
V
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as V
Reference clock (PLL) input Pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A, B, C...at each side.
Optional feedback (PLL) input Pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A, B, C...at each side.
Primary Clock Pads, T = true and C = complement, n per side, indexed by
bank and 0,1, 2, 3 within bank.
DQS input Pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = Ball
function number. Any pad can be configured to be DQS output.
CCAUX
CCIO
- The power supply pins for I/O bank x. Dedicated Pins.
- The Auxiliary power supply pin. It powers all the differential and ref-
LatticeXP Family Data Sheet
4-1
REF
inputs. When not used, they may be used as I/O pins.
Descriptions
Pinout Information
1
).
1
).
1
).
1
).
DS1001
Data Sheet DS1001
Pinouts_02.5